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80c6397c37
The Kconfig currently controlling compilation of this code is: drivers/clk/Kconfig:config COMMON_CLK_OXNAS drivers/clk/Kconfig: bool "Clock driver for the OXNAS SoC Family" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. Cc: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-6-paul.gortmaker@windriver.com
187 lines
4.8 KiB
C
187 lines
4.8 KiB
C
/*
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* Copyright (C) 2010 Broadcom
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* Copyright (C) 2012 Stephen Warren
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/stringify.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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/* Standard regmap gate clocks */
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struct clk_oxnas {
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struct clk_hw hw;
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signed char bit;
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struct regmap *regmap;
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};
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/* Regmap offsets */
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#define CLK_STAT_REGOFFSET 0x24
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#define CLK_SET_REGOFFSET 0x2c
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#define CLK_CLR_REGOFFSET 0x30
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static inline struct clk_oxnas *to_clk_oxnas(struct clk_hw *hw)
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{
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return container_of(hw, struct clk_oxnas, hw);
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}
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static int oxnas_clk_is_enabled(struct clk_hw *hw)
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{
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struct clk_oxnas *std = to_clk_oxnas(hw);
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int ret;
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unsigned int val;
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ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val);
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if (ret < 0)
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return ret;
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return val & BIT(std->bit);
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}
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static int oxnas_clk_enable(struct clk_hw *hw)
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{
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struct clk_oxnas *std = to_clk_oxnas(hw);
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regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit));
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return 0;
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}
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static void oxnas_clk_disable(struct clk_hw *hw)
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{
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struct clk_oxnas *std = to_clk_oxnas(hw);
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regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit));
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}
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static const struct clk_ops oxnas_clk_ops = {
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.enable = oxnas_clk_enable,
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.disable = oxnas_clk_disable,
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.is_enabled = oxnas_clk_is_enabled,
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};
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static const char *const oxnas_clk_parents[] = {
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"oscillator",
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};
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static const char *const eth_parents[] = {
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"gmacclk",
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};
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#define DECLARE_STD_CLKP(__clk, __parent) \
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static const struct clk_init_data clk_##__clk##_init = { \
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.name = __stringify(__clk), \
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.ops = &oxnas_clk_ops, \
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.parent_names = __parent, \
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.num_parents = ARRAY_SIZE(__parent), \
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}
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#define DECLARE_STD_CLK(__clk) DECLARE_STD_CLKP(__clk, oxnas_clk_parents)
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/* Hardware Bit - Clock association */
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struct clk_oxnas_init_data {
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unsigned long bit;
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const struct clk_init_data *clk_init;
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};
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/* Clk init data declaration */
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DECLARE_STD_CLK(leon);
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DECLARE_STD_CLK(dma_sgdma);
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DECLARE_STD_CLK(cipher);
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DECLARE_STD_CLK(sata);
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DECLARE_STD_CLK(audio);
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DECLARE_STD_CLK(usbmph);
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DECLARE_STD_CLKP(etha, eth_parents);
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DECLARE_STD_CLK(pciea);
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DECLARE_STD_CLK(nand);
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/* Table index is clock indice */
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static const struct clk_oxnas_init_data clk_oxnas_init[] = {
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[0] = {0, &clk_leon_init},
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[1] = {1, &clk_dma_sgdma_init},
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[2] = {2, &clk_cipher_init},
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/* Skip & Do not touch to DDR clock */
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[3] = {4, &clk_sata_init},
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[4] = {5, &clk_audio_init},
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[5] = {6, &clk_usbmph_init},
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[6] = {7, &clk_etha_init},
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[7] = {8, &clk_pciea_init},
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[8] = {9, &clk_nand_init},
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};
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struct clk_oxnas_data {
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struct clk_oxnas clk_oxnas[ARRAY_SIZE(clk_oxnas_init)];
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struct clk_onecell_data onecell_data[ARRAY_SIZE(clk_oxnas_init)];
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struct clk *clks[ARRAY_SIZE(clk_oxnas_init)];
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};
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static int oxnas_stdclk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct clk_oxnas_data *clk_oxnas;
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struct regmap *regmap;
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int i;
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clk_oxnas = devm_kzalloc(&pdev->dev, sizeof(*clk_oxnas), GFP_KERNEL);
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if (!clk_oxnas)
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return -ENOMEM;
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regmap = syscon_node_to_regmap(of_get_parent(np));
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if (IS_ERR(regmap)) {
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dev_err(&pdev->dev, "failed to have parent regmap\n");
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return PTR_ERR(regmap);
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}
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for (i = 0; i < ARRAY_SIZE(clk_oxnas_init); i++) {
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struct clk_oxnas *_clk;
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_clk = &clk_oxnas->clk_oxnas[i];
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_clk->bit = clk_oxnas_init[i].bit;
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_clk->hw.init = clk_oxnas_init[i].clk_init;
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_clk->regmap = regmap;
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clk_oxnas->clks[i] =
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devm_clk_register(&pdev->dev, &_clk->hw);
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if (WARN_ON(IS_ERR(clk_oxnas->clks[i])))
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return PTR_ERR(clk_oxnas->clks[i]);
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}
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clk_oxnas->onecell_data->clks = clk_oxnas->clks;
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clk_oxnas->onecell_data->clk_num = ARRAY_SIZE(clk_oxnas_init);
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return of_clk_add_provider(np, of_clk_src_onecell_get,
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clk_oxnas->onecell_data);
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}
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static const struct of_device_id oxnas_stdclk_dt_ids[] = {
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{ .compatible = "oxsemi,ox810se-stdclk" },
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{ }
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};
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static struct platform_driver oxnas_stdclk_driver = {
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.probe = oxnas_stdclk_probe,
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.driver = {
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.name = "oxnas-stdclk",
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.suppress_bind_attrs = true,
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.of_match_table = oxnas_stdclk_dt_ids,
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},
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};
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builtin_platform_driver(oxnas_stdclk_driver);
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