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e2c5eb78a3
The GPMC binding is obviously very confusing as the values are all over the place. People seem to confuse the GPMC partition size for the chip select, and the device IO size within the GPMC partition easily. The ranges entry contains the GPMC partition size. And the reg entry contains the size of the IO registers of the device connected to the GPMC. Let's fix the issue according to the following table: Device GPMC partition size Device IO size connected in the ranges entry in the reg entry NAND 0x01000000 (16MB) 4 16550 0x01000000 (16MB) 8 smc91x 0x01000000 (16MB) 0xf smc911x 0x01000000 (16MB) 0xff OneNAND 0x01000000 (16MB) 0x20000 (128KB) 16MB NOR 0x01000000 (16MB) 0x01000000 (16MB) 32MB NOR 0x02000000 (32MB) 0x02000000 (32MB) 64MB NOR 0x04000000 (64MB) 0x04000000 (64MB) 128MB NOR 0x08000000 (128MB) 0x08000000 (128MB) 256MB NOR 0x10000000 (256MB) 0x10000000 (256MB) Let's also add comments to the fixed entries while at it. Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
338 lines
9.1 KiB
Plaintext
338 lines
9.1 KiB
Plaintext
/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "omap34xx-hs.dtsi"
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/ {
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cpus {
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cpu@0 {
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cpu0-supply = <&vcc>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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/* HS USB Port 2 Power */
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hsusb2_power: hsusb2_power_reg {
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compatible = "regulator-fixed";
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regulator-name = "hsusb2_vbus";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
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startup-delay-us = <70000>;
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};
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/* HS USB Host PHY on PORT 2 */
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hsusb2_phy: hsusb2_phy {
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compatible = "usb-nop-xceiv";
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reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */
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vcc-supply = <&hsusb2_power>;
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};
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sound {
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compatible = "ti,omap-twl4030";
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ti,model = "omap3beagle";
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/* McBSP2 is used for onboard sound, same as on beagle */
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ti,mcbsp = <&mcbsp2>;
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ti,codec = <&twl_audio>;
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};
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/* Regulator to enable/switch the vcc of the Wifi module */
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mmc2_sdio_poweron: regulator-mmc2-sdio-poweron {
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compatible = "regulator-fixed";
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regulator-name = "regulator-mmc2-sdio-poweron";
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regulator-min-microvolt = <3150000>;
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regulator-max-microvolt = <3150000>;
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gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */
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enable-active-low;
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startup-delay-us = <10000>;
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};
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};
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&omap3_pmx_core {
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hsusbb2_pins: pinmux_hsusbb2_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
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OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
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OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
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OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
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OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
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OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
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OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
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OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
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OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
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OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
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OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
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OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
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>;
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};
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
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OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
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OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
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OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
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OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
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OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
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OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
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OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
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OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
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OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
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>;
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};
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mmc2_pins: pinmux_mmc2_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
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OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
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OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
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OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
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OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
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OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
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>;
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};
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/* wlan GPIO output for WLAN_EN */
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wlan_gpio: pinmux_wlan_gpio {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */
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>;
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};
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uart3_pins: pinmux_uart3_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
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OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
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>;
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};
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i2c3_pins: pinmux_i2c3_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */
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OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */
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>;
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};
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mcspi1_pins: pinmux_mcspi1_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
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OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
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OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
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OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
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>;
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};
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mcspi3_pins: pinmux_mcspi3_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */
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OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */
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OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */
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OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */
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>;
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};
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mcbsp3_pins: pinmux_mcbsp3_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */
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OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */
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OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */
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OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */
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>;
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};
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};
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/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */
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&mcbsp1 {
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status = "disabled";
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};
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&mcbsp2 {
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <2600000>;
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twl: twl@48 {
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reg = <0x48>;
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interrupts = <7>; /* SYS_NIRQ cascaded to intc */
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interrupt-parent = <&intc>;
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twl_audio: audio {
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compatible = "ti,twl4030-audio";
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codec {
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};
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};
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};
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_pins>;
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};
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&mcspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcspi1_pins>;
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spidev@0 {
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compatible = "spidev";
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spi-max-frequency = <48000000>;
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reg = <0>;
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spi-cpha;
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};
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};
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&mcspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcspi3_pins>;
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spidev@0 {
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compatible = "spidev";
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spi-max-frequency = <48000000>;
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reg = <0>;
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spi-cpha;
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};
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};
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#include "twl4030.dtsi"
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#include "twl4030_omap3.dtsi"
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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vmmc-supply = <&vmmc1>;
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vmmc_aux-supply = <&vsim>;
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cd-gpios = <&twl_gpio 0 0>;
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bus-width = <8>;
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};
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// WiFi (Marvell 88W8686) on MMC2/SDIO
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&mmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_pins>;
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vmmc-supply = <&mmc2_sdio_poweron>;
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non-removable;
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bus-width = <4>;
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cap-power-off-card;
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};
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&mmc3 {
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status = "disabled";
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};
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&usbhshost {
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port2-mode = "ehci-phy";
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};
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&usbhsehci {
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phys = <0 &hsusb2_phy>;
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};
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&twl_gpio {
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ti,use-leds;
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/* pullups: BIT(1) */
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ti,pullups = <0x000002>;
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/*
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* pulldowns:
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* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
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* BIT(15), BIT(16), BIT(17)
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*/
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ti,pulldowns = <0x03a1c4>;
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pins>;
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};
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&mcbsp3 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mcbsp3_pins>;
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};
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&gpmc {
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ranges = <0 0 0x00000000 0x01000000>;
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nand@0,0 {
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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nand-bus-width = <16>;
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gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
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ti,nand-ecc-opt = "sw";
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <36>;
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gpmc,cs-wr-off-ns = <36>;
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gpmc,adv-on-ns = <6>;
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gpmc,adv-rd-off-ns = <24>;
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gpmc,adv-wr-off-ns = <36>;
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gpmc,oe-on-ns = <6>;
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gpmc,oe-off-ns = <48>;
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gpmc,we-on-ns = <6>;
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gpmc,we-off-ns = <30>;
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gpmc,rd-cycle-ns = <72>;
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gpmc,wr-cycle-ns = <72>;
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gpmc,access-ns = <54>;
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gpmc,wr-access-ns = <30>;
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#address-cells = <1>;
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#size-cells = <1>;
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x-loader@0 {
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label = "X-Loader";
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reg = <0 0x80000>;
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};
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bootloaders@80000 {
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label = "U-Boot";
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reg = <0x80000 0x1e0000>;
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};
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bootloaders_env@260000 {
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label = "U-Boot Env";
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reg = <0x260000 0x20000>;
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};
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kernel@280000 {
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label = "Kernel";
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reg = <0x280000 0x400000>;
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};
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filesystem@680000 {
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label = "File System";
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reg = <0x680000 0xf980000>;
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};
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};
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};
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&usb_otg_hs {
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interface-type = <0>;
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usb-phy = <&usb2_phy>;
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phys = <&usb2_phy>;
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phy-names = "usb2-phy";
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mode = <3>;
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power = <50>;
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};
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&vaux2 {
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regulator-name = "vdd_ehci";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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