mirror of
https://github.com/torvalds/linux.git
synced 2024-11-07 20:51:47 +00:00
facf47ee6b
For imx27, it needs three clocks to let the controller work, the old code is wrong, and usbmisc has not included clock handling code any more. Without this patch, it will cause below data abort when accessing usbmisc registers. usbcore: registered new interface driver usb-storage Unhandled fault: external abort on non-linefetch (0x008) at 0xf4424600 pgd = c0004000 [f4424600] *pgd=10000452(bad) Internal error: : 8 [#1] PREEMPT ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper Not tainted 4.1.0-next-20150701-dirty #3089 Hardware name: Freescale i.MX27 (Device Tree Support) task: c7832b60 ti: c783e000 task.ti: c783e000 PC is at usbmisc_imx27_init+0x4c/0xbc LR is at usbmisc_imx27_init+0x40/0xbc pc : [<c03cb5c0>] lr : [<c03cb5b4>] psr: 60000093 sp : c783fe08 ip : 00000000 fp : 00000000 r10: c0576434 r9 : 0000009c r8 : c7a773a0 r7 : 01000000 r6 : 60000013 r5 : c7a776f0 r4 : c7a773f0 r3 : f4424600 r2 : 00000000 r1 : 00000001 r0 : 00000001 Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 0005317f Table: a0004000 DAC: 00000017 Process swapper (pid: 1, stack limit = 0xc783e190) Stack: (0xc783fe08 to 0xc7840000) Signed-off-by: Peter Chen <peter.chen@freescale.com> Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Cc: <stable@vger.kernel.org> #v4.1+ Acked-by: Shawn Guo <shawnguo@kernel.org>
595 lines
15 KiB
Plaintext
595 lines
15 KiB
Plaintext
/*
|
|
* Copyright 2012 Sascha Hauer, Pengutronix
|
|
*
|
|
* The code contained herein is licensed under the GNU General Public
|
|
* License. You may obtain a copy of the GNU General Public License
|
|
* Version 2 or later at the following locations:
|
|
*
|
|
* http://www.opensource.org/licenses/gpl-license.html
|
|
* http://www.gnu.org/copyleft/gpl.html
|
|
*/
|
|
|
|
#include "skeleton.dtsi"
|
|
#include "imx27-pinfunc.h"
|
|
|
|
#include <dt-bindings/clock/imx27-clock.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
|
|
/ {
|
|
aliases {
|
|
ethernet0 = &fec;
|
|
gpio0 = &gpio1;
|
|
gpio1 = &gpio2;
|
|
gpio2 = &gpio3;
|
|
gpio3 = &gpio4;
|
|
gpio4 = &gpio5;
|
|
gpio5 = &gpio6;
|
|
i2c0 = &i2c1;
|
|
i2c1 = &i2c2;
|
|
serial0 = &uart1;
|
|
serial1 = &uart2;
|
|
serial2 = &uart3;
|
|
serial3 = &uart4;
|
|
serial4 = &uart5;
|
|
serial5 = &uart6;
|
|
spi0 = &cspi1;
|
|
spi1 = &cspi2;
|
|
spi2 = &cspi3;
|
|
};
|
|
|
|
aitc: aitc-interrupt-controller@e0000000 {
|
|
compatible = "fsl,imx27-aitc", "fsl,avic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x10040000 0x1000>;
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
osc26m {
|
|
compatible = "fsl,imx-osc26m", "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <26000000>;
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
#size-cells = <0>;
|
|
#address-cells = <1>;
|
|
|
|
cpu: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,arm926ej-s";
|
|
operating-points = <
|
|
/* kHz uV */
|
|
266000 1300000
|
|
399000 1450000
|
|
>;
|
|
clock-latency = <62500>;
|
|
clocks = <&clks IMX27_CLK_CPU_DIV>;
|
|
voltage-tolerance = <5>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
interrupt-parent = <&aitc>;
|
|
ranges;
|
|
|
|
aipi@10000000 { /* AIPI1 */
|
|
compatible = "fsl,aipi-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x10000000 0x20000>;
|
|
ranges;
|
|
|
|
dma: dma@10001000 {
|
|
compatible = "fsl,imx27-dma";
|
|
reg = <0x10001000 0x1000>;
|
|
interrupts = <32>;
|
|
clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
|
|
<&clks IMX27_CLK_DMA_AHB_GATE>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <1>;
|
|
#dma-channels = <16>;
|
|
};
|
|
|
|
wdog: wdog@10002000 {
|
|
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
|
|
reg = <0x10002000 0x1000>;
|
|
interrupts = <27>;
|
|
clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
|
|
};
|
|
|
|
gpt1: timer@10003000 {
|
|
compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
|
|
reg = <0x10003000 0x1000>;
|
|
interrupts = <26>;
|
|
clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
gpt2: timer@10004000 {
|
|
compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
|
|
reg = <0x10004000 0x1000>;
|
|
interrupts = <25>;
|
|
clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
gpt3: timer@10005000 {
|
|
compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
|
|
reg = <0x10005000 0x1000>;
|
|
interrupts = <24>;
|
|
clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
pwm: pwm@10006000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx27-pwm";
|
|
reg = <0x10006000 0x1000>;
|
|
interrupts = <23>;
|
|
clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
rtc: rtc@10007000 {
|
|
compatible = "fsl,imx21-rtc";
|
|
reg = <0x10007000 0x1000>;
|
|
interrupts = <22>;
|
|
clocks = <&clks IMX27_CLK_CKIL>,
|
|
<&clks IMX27_CLK_RTC_IPG_GATE>;
|
|
clock-names = "ref", "ipg";
|
|
};
|
|
|
|
kpp: kpp@10008000 {
|
|
compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
|
|
reg = <0x10008000 0x1000>;
|
|
interrupts = <21>;
|
|
clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
owire: owire@10009000 {
|
|
compatible = "fsl,imx27-owire", "fsl,imx21-owire";
|
|
reg = <0x10009000 0x1000>;
|
|
clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@1000a000 {
|
|
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
|
reg = <0x1000a000 0x1000>;
|
|
interrupts = <20>;
|
|
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@1000b000 {
|
|
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
|
reg = <0x1000b000 0x1000>;
|
|
interrupts = <19>;
|
|
clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@1000c000 {
|
|
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
|
reg = <0x1000c000 0x1000>;
|
|
interrupts = <18>;
|
|
clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@1000d000 {
|
|
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
|
reg = <0x1000d000 0x1000>;
|
|
interrupts = <17>;
|
|
clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
cspi1: cspi@1000e000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx27-cspi";
|
|
reg = <0x1000e000 0x1000>;
|
|
interrupts = <16>;
|
|
clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER2_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
cspi2: cspi@1000f000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx27-cspi";
|
|
reg = <0x1000f000 0x1000>;
|
|
interrupts = <15>;
|
|
clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER2_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi1: ssi@10010000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
|
|
reg = <0x10010000 0x1000>;
|
|
interrupts = <14>;
|
|
clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
|
|
dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
|
|
dma-names = "rx0", "tx0", "rx1", "tx1";
|
|
fsl,fifo-depth = <8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi2: ssi@10011000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
|
|
reg = <0x10011000 0x1000>;
|
|
interrupts = <13>;
|
|
clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
|
|
dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
|
|
dma-names = "rx0", "tx0", "rx1", "tx1";
|
|
fsl,fifo-depth = <8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@10012000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
|
|
reg = <0x10012000 0x1000>;
|
|
interrupts = <12>;
|
|
clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci1: sdhci@10013000 {
|
|
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
|
|
reg = <0x10013000 0x1000>;
|
|
interrupts = <11>;
|
|
clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER2_GATE>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&dma 7>;
|
|
dma-names = "rx-tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci2: sdhci@10014000 {
|
|
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
|
|
reg = <0x10014000 0x1000>;
|
|
interrupts = <10>;
|
|
clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER2_GATE>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&dma 6>;
|
|
dma-names = "rx-tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
iomuxc: iomuxc@10015000 {
|
|
compatible = "fsl,imx27-iomuxc";
|
|
reg = <0x10015000 0x600>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
gpio1: gpio@10015000 {
|
|
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
|
reg = <0x10015000 0x100>;
|
|
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
|
interrupts = <8>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@10015100 {
|
|
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
|
reg = <0x10015100 0x100>;
|
|
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
|
interrupts = <8>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@10015200 {
|
|
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
|
reg = <0x10015200 0x100>;
|
|
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
|
interrupts = <8>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio@10015300 {
|
|
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
|
reg = <0x10015300 0x100>;
|
|
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
|
interrupts = <8>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio5: gpio@10015400 {
|
|
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
|
reg = <0x10015400 0x100>;
|
|
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
|
interrupts = <8>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio6: gpio@10015500 {
|
|
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
|
reg = <0x10015500 0x100>;
|
|
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
|
interrupts = <8>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
audmux: audmux@10016000 {
|
|
compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
|
|
reg = <0x10016000 0x1000>;
|
|
clocks = <&clks IMX27_CLK_DUMMY>;
|
|
clock-names = "audmux";
|
|
status = "disabled";
|
|
};
|
|
|
|
cspi3: cspi@10017000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx27-cspi";
|
|
reg = <0x10017000 0x1000>;
|
|
interrupts = <6>;
|
|
clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER2_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpt4: timer@10019000 {
|
|
compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
|
|
reg = <0x10019000 0x1000>;
|
|
interrupts = <4>;
|
|
clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
gpt5: timer@1001a000 {
|
|
compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
|
|
reg = <0x1001a000 0x1000>;
|
|
interrupts = <3>;
|
|
clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
uart5: serial@1001b000 {
|
|
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
|
reg = <0x1001b000 0x1000>;
|
|
interrupts = <49>;
|
|
clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@1001c000 {
|
|
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
|
reg = <0x1001c000 0x1000>;
|
|
interrupts = <48>;
|
|
clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@1001d000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
|
|
reg = <0x1001d000 0x1000>;
|
|
interrupts = <1>;
|
|
clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci3: sdhci@1001e000 {
|
|
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
|
|
reg = <0x1001e000 0x1000>;
|
|
interrupts = <9>;
|
|
clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER2_GATE>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&dma 36>;
|
|
dma-names = "rx-tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpt6: timer@1001f000 {
|
|
compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
|
|
reg = <0x1001f000 0x1000>;
|
|
interrupts = <2>;
|
|
clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
};
|
|
|
|
aipi@10020000 { /* AIPI2 */
|
|
compatible = "fsl,aipi-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x10020000 0x20000>;
|
|
ranges;
|
|
|
|
fb: fb@10021000 {
|
|
compatible = "fsl,imx27-fb", "fsl,imx21-fb";
|
|
interrupts = <61>;
|
|
reg = <0x10021000 0x1000>;
|
|
clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
|
|
<&clks IMX27_CLK_LCDC_AHB_GATE>,
|
|
<&clks IMX27_CLK_PER3_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
coda: coda@10023000 {
|
|
compatible = "fsl,imx27-vpu", "cnm,codadx6";
|
|
reg = <0x10023000 0x0200>;
|
|
interrupts = <53>;
|
|
clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
|
|
<&clks IMX27_CLK_VPU_AHB_GATE>;
|
|
clock-names = "per", "ahb";
|
|
iram = <&iram>;
|
|
};
|
|
|
|
usbotg: usb@10024000 {
|
|
compatible = "fsl,imx27-usb";
|
|
reg = <0x10024000 0x200>;
|
|
interrupts = <56>;
|
|
clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
|
|
<&clks IMX27_CLK_USB_AHB_GATE>,
|
|
<&clks IMX27_CLK_USB_DIV>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
fsl,usbmisc = <&usbmisc 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh1: usb@10024200 {
|
|
compatible = "fsl,imx27-usb";
|
|
reg = <0x10024200 0x200>;
|
|
interrupts = <54>;
|
|
clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
|
|
<&clks IMX27_CLK_USB_AHB_GATE>,
|
|
<&clks IMX27_CLK_USB_DIV>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
fsl,usbmisc = <&usbmisc 1>;
|
|
dr_mode = "host";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh2: usb@10024400 {
|
|
compatible = "fsl,imx27-usb";
|
|
reg = <0x10024400 0x200>;
|
|
interrupts = <55>;
|
|
clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
|
|
<&clks IMX27_CLK_USB_AHB_GATE>,
|
|
<&clks IMX27_CLK_USB_DIV>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
fsl,usbmisc = <&usbmisc 2>;
|
|
dr_mode = "host";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc: usbmisc@10024600 {
|
|
#index-cells = <1>;
|
|
compatible = "fsl,imx27-usbmisc";
|
|
reg = <0x10024600 0x200>;
|
|
};
|
|
|
|
sahara2: sahara@10025000 {
|
|
compatible = "fsl,imx27-sahara";
|
|
reg = <0x10025000 0x1000>;
|
|
interrupts = <59>;
|
|
clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
|
|
<&clks IMX27_CLK_SAHARA_AHB_GATE>;
|
|
clock-names = "ipg", "ahb";
|
|
};
|
|
|
|
clks: ccm@10027000{
|
|
compatible = "fsl,imx27-ccm";
|
|
reg = <0x10027000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
iim: iim@10028000 {
|
|
compatible = "fsl,imx27-iim";
|
|
reg = <0x10028000 0x1000>;
|
|
interrupts = <62>;
|
|
clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
|
|
};
|
|
|
|
fec: ethernet@1002b000 {
|
|
compatible = "fsl,imx27-fec";
|
|
reg = <0x1002b000 0x1000>;
|
|
interrupts = <50>;
|
|
clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
|
|
<&clks IMX27_CLK_FEC_AHB_GATE>;
|
|
clock-names = "ipg", "ahb";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
nfc: nand@d8000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,imx27-nand";
|
|
reg = <0xd8000000 0x1000>;
|
|
interrupts = <29>;
|
|
clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
weim: weim@d8002000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,imx27-weim";
|
|
reg = <0xd8002000 0x1000>;
|
|
clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
|
|
ranges = <
|
|
0 0 0xc0000000 0x08000000
|
|
1 0 0xc8000000 0x08000000
|
|
2 0 0xd0000000 0x02000000
|
|
3 0 0xd2000000 0x02000000
|
|
4 0 0xd4000000 0x02000000
|
|
5 0 0xd6000000 0x02000000
|
|
>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iram: iram@ffff4c00 {
|
|
compatible = "mmio-sram";
|
|
reg = <0xffff4c00 0xb400>;
|
|
};
|
|
};
|
|
};
|