Luke Nelson 804ec72c68 bpf, riscv: Add encodings for compressed instructions ... This patch adds functions for encoding and emitting compressed riscv (RVC) instructions to the BPF JIT. Some regular riscv instructions can be compressed into an RVC instruction if the instruction fields meet some requirements. For example, "add rd, rs1, rs2" can be compressed into "c.add rd, rs2" when rd == rs1. To make using RVC encodings simpler, this patch also adds helper functions that selectively emit either a regular instruction or a compressed instruction if possible. For example, emit_add will produce a "c.add" if possible and regular "add" otherwise. Signed-off-by: Luke Nelson <luke.r.nels@gmail.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org> Link: https://lore.kernel.org/bpf/20200721025241.8077-3-luke.r.nels@gmail.com		2020-07-21 13:26:25 -07:00
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bpf_jit_comp32.c	bpf, riscv: Modify JIT ctx to support compressed instructions	2020-07-21 13:26:25 -07:00
bpf_jit_comp64.c	bpf, riscv: Modify JIT ctx to support compressed instructions	2020-07-21 13:26:25 -07:00
bpf_jit_core.c	bpf, riscv: Modify JIT ctx to support compressed instructions	2020-07-21 13:26:25 -07:00
bpf_jit.h	bpf, riscv: Add encodings for compressed instructions	2020-07-21 13:26:25 -07:00
Makefile	riscv, bpf: Add RV32G eBPF JIT	2020-03-05 16:13:47 +01:00