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rs485 allows for robust half-duplex serial communication. It is often implemented by attaching an rs485 transceiver to a UART. The UART's RTS line is wired to the transceiver's Transmit Enable pin and determines whether the transceiver is sending or receiving. Examples for such transceivers are Maxim MAX13451E and TI SN65HVD1781A: https://datasheets.maximintegrated.com/en/ds/MAX13450E-MAX13451E.pdf http://www.ti.com/lit/ds/symlink/sn65hvd1781a-q1.pdf In the devicetree, the transceiver itself is not represented, only the UART is. A few rs485-specific dt-bindings already exist and these go into the UART's device node. This commit adds a binding to set the RTS polarity. Most (if not all) transceivers require the Transmit Enable pin be driven high for sending, but in some cases boards may negate the pin and RTS must then be driven low. Consequently the polarity defaults to active high but can be inverted with the newly added "rs485-rts-active-low" binding. Document this binding in rs485.txt and in the two drivers fsl-imx-uart and fsl-lpuart that are about to be amended with support for it. Curiously, the omap_serial driver defaults to active low and already supports an "rs485-rts-active-high" binding to invert the polarity. This is left unchanged to retain compatibility, but the binding is herewith documented. Cc: Mark Jackson <mpfj@newflow.co.uk> Cc: Michał Oleszczyk <oleszczyk.m@gmail.com> Cc: Rafael Gago Castano <rgc@hms.se> Cc: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lukas Wunner <lukas@wunner.de> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
36 lines
1.3 KiB
Plaintext
36 lines
1.3 KiB
Plaintext
* Freescale low power universal asynchronous receiver/transmitter (lpuart)
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Required properties:
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- compatible :
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- "fsl,vf610-lpuart" for lpuart compatible with the one integrated
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on Vybrid vf610 SoC with 8-bit register organization
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- "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
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on LS1021A SoC with 32-bit big-endian register organization
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- "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated
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on i.MX7ULP SoC with 32-bit little-endian register organization
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- reg : Address and length of the register set for the device
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- interrupts : Should contain uart interrupt
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- clocks : phandle + clock specifier pairs, one for each entry in clock-names
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- clock-names : should contain: "ipg" - the uart clock
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Optional properties:
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- dmas: A list of two dma specifiers, one for each entry in dma-names.
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- dma-names: should contain "tx" and "rx".
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- rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
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linux,rs485-enabled-at-boot-time: see rs485.txt
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Note: Optional properties for DMA support. Write them both or both not.
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Example:
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uart0: serial@40027000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x40027000 0x1000>;
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interrupts = <0 61 0x00>;
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clocks = <&clks VF610_CLK_UART0>;
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clock-names = "ipg";
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dmas = <&edma0 0 2>,
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<&edma0 0 3>;
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dma-names = "rx","tx";
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};
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