mirror of
https://github.com/torvalds/linux.git
synced 2024-11-14 16:12:02 +00:00
10c8e05620
A handful of driver-related changes. We've had a bunch of them going in through
other branches as well, so it's only a part of what we really have this release.
Larger pieces are:
* Removal of a now unused PWM driver for atmel
- This includes AVR32 changes that have been appropriately acked.
* Performance counter support for the arm CCN interconnect
* OMAP mailbox driver cleanups and consolidation
* PCI and SATA PHY drivers for SPEAr 13xx platforms
* Redefinition (with backwards compatibility!) of PCI DT bindings for Tegra to
better model regulators/power.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJT5DrJAAoJEIwa5zzehBx3wkkP/iwEfEK5mMon9KEe4DcKTKNq
Z6xyWuMQNHKdfBFpABs6AsHQCKDc7KK6gN3+2zLLHEJ4XGDPZ2g2NaX3oRPJlaay
BDK7rQfIZyi4tmbOnlEv1BDTYgirYBPMwk9RyNo/04Ug3W+Y67aSVo44zkNFBWaJ
GbcX/zYsrsfvdawuQMW6V/A835s3Kq5Zhv1ikPr8gDDjswZRBAT6i7FYpBSHQ8K8
bH6C1891Xit6rxXSLXJyrtM8CAet7PtLTqNr/IKdUaJnGD+fJm5EonxW+g8gvhN8
gOEkm3nM60++kdDlzZCQVNr0m1+ih6NNCr6bDLO6rIRpAJM2O+YrN1rWuZaJOu1A
pIvifk+wWHT+o52pXk8g9fK4n/ZJydK3IBzDePHMrIROOEiW5tLE3WA+u3NSfMfH
WegMt9E2dcB+5gXPeejZ9gFbAHnh2S1oVTZfCYXtuOHrYiEU9U0FA3eRYvJEE2po
k8sdiOn7Vc65O1QZ+xZNbLABpAHaye7X2evOJyhSutzHE/AtUvT4vuCAZ0tggXyD
E1qVKngVW/NvcoFbwYeidq4bOVgiAEn3idZgF5gEq1mq7LzetXUQAcZAOQfLWHLQ
RrXufS7Ez8pSCG74y0AFReVfQH2PgWHPqGUGj99NXgQauexc/vR1Hc5Iqb8liGNJ
n6i8RqvvQ4KYcmHEXDIT
=fsP6
-----END PGP SIGNATURE-----
Merge tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson:
"A handful of driver-related changes. We've had a bunch of them going
in through other branches as well, so it's only a part of what we
really have this release.
Larger pieces are:
- Removal of a now unused PWM driver for atmel
[ This includes AVR32 changes that have been appropriately acked ]
- Performance counter support for the arm CCN interconnect
- OMAP mailbox driver cleanups and consolidation
- PCI and SATA PHY drivers for SPEAr 13xx platforms
- Redefinition (with backwards compatibility!) of PCI DT bindings for
Tegra to better model regulators/power"
Note: this merge also fixes up the semantic conflict with the new
calling convention for devm_phy_create(), see commit f0ed817638 ("phy:
core: Let node ptr of PHY point to PHY and not of PHY provider") that
came in through Greg's USB tree.
Semantic merge patch by Stephen Rothwell <sfr@canb.auug.org.au> through
the next tree.
* tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits)
bus: arm-ccn: Fix error handling at event allocation
mailbox/omap: add a parent structure for every IP instance
mailbox/omap: remove the private mailbox structure
mailbox/omap: consolidate OMAP mailbox driver
mailbox/omap: simplify the fifo assignment by using macros
mailbox/omap: remove omap_mbox_type_t from mailbox ops
mailbox/omap: remove OMAP1 mailbox driver
mailbox/omap: use devm_* interfaces
bus: ARM CCN: add PERF_EVENTS dependency
bus: ARM CCN PMU driver
PCI: spear: Remove spear13xx_pcie_remove()
PCI: spear: Fix Section mismatch compilation warning for probe()
ARM: tegra: Remove legacy PCIe power supply properties
PCI: tegra: Remove deprecated power supply properties
PCI: tegra: Implement accurate power supply scheme
ARM: SPEAr13xx: Update defconfigs
ARM: SPEAr13xx: Add pcie and miphy DT nodes
ARM: SPEAr13xx: Add bindings and dt node for misc block
ARM: SPEAr13xx: Fix static mapping table
phy: Add drivers for PCIe and SATA phy on SPEAr13xx
...
529 lines
11 KiB
Plaintext
529 lines
11 KiB
Plaintext
#include "tegra20.dtsi"
|
|
|
|
/ {
|
|
model = "Avionic Design Tamonten SOM";
|
|
compatible = "ad,tamonten", "nvidia,tegra20";
|
|
|
|
aliases {
|
|
rtc0 = "/i2c@7000d000/tps6586x@34";
|
|
rtc1 = "/rtc@7000e000";
|
|
};
|
|
|
|
memory {
|
|
reg = <0x00000000 0x20000000>;
|
|
};
|
|
|
|
host1x@50000000 {
|
|
hdmi@54280000 {
|
|
vdd-supply = <&hdmi_vdd_reg>;
|
|
pll-supply = <&hdmi_pll_reg>;
|
|
|
|
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
|
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
|
|
GPIO_ACTIVE_HIGH>;
|
|
};
|
|
};
|
|
|
|
pinmux@70000014 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&state_default>;
|
|
|
|
state_default: pinmux {
|
|
ata {
|
|
nvidia,pins = "ata";
|
|
nvidia,function = "ide";
|
|
};
|
|
atb {
|
|
nvidia,pins = "atb", "gma", "gme";
|
|
nvidia,function = "sdio4";
|
|
};
|
|
atc {
|
|
nvidia,pins = "atc";
|
|
nvidia,function = "nand";
|
|
};
|
|
atd {
|
|
nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
|
|
"spia", "spib", "spic";
|
|
nvidia,function = "gmi";
|
|
};
|
|
cdev1 {
|
|
nvidia,pins = "cdev1";
|
|
nvidia,function = "plla_out";
|
|
};
|
|
cdev2 {
|
|
nvidia,pins = "cdev2";
|
|
nvidia,function = "pllp_out4";
|
|
};
|
|
crtp {
|
|
nvidia,pins = "crtp";
|
|
nvidia,function = "crt";
|
|
};
|
|
csus {
|
|
nvidia,pins = "csus";
|
|
nvidia,function = "vi_sensor_clk";
|
|
};
|
|
dap1 {
|
|
nvidia,pins = "dap1";
|
|
nvidia,function = "dap1";
|
|
};
|
|
dap2 {
|
|
nvidia,pins = "dap2";
|
|
nvidia,function = "dap2";
|
|
};
|
|
dap3 {
|
|
nvidia,pins = "dap3";
|
|
nvidia,function = "dap3";
|
|
};
|
|
dap4 {
|
|
nvidia,pins = "dap4";
|
|
nvidia,function = "dap4";
|
|
};
|
|
dta {
|
|
nvidia,pins = "dta", "dtd";
|
|
nvidia,function = "sdio2";
|
|
};
|
|
dtb {
|
|
nvidia,pins = "dtb", "dtc", "dte";
|
|
nvidia,function = "rsvd1";
|
|
};
|
|
dtf {
|
|
nvidia,pins = "dtf";
|
|
nvidia,function = "i2c3";
|
|
};
|
|
gmc {
|
|
nvidia,pins = "gmc";
|
|
nvidia,function = "uartd";
|
|
};
|
|
gpu7 {
|
|
nvidia,pins = "gpu7";
|
|
nvidia,function = "rtck";
|
|
};
|
|
gpv {
|
|
nvidia,pins = "gpv", "slxa", "slxk";
|
|
nvidia,function = "pcie";
|
|
};
|
|
hdint {
|
|
nvidia,pins = "hdint";
|
|
nvidia,function = "hdmi";
|
|
};
|
|
i2cp {
|
|
nvidia,pins = "i2cp";
|
|
nvidia,function = "i2cp";
|
|
};
|
|
irrx {
|
|
nvidia,pins = "irrx", "irtx";
|
|
nvidia,function = "uarta";
|
|
};
|
|
kbca {
|
|
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
|
"kbce", "kbcf";
|
|
nvidia,function = "kbc";
|
|
};
|
|
lcsn {
|
|
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
|
|
"ld3", "ld4", "ld5", "ld6", "ld7",
|
|
"ld8", "ld9", "ld10", "ld11", "ld12",
|
|
"ld13", "ld14", "ld15", "ld16", "ld17",
|
|
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
|
|
"lhs", "lm0", "lm1", "lpp", "lpw0",
|
|
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
|
|
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
|
|
"lvs";
|
|
nvidia,function = "displaya";
|
|
};
|
|
owc {
|
|
nvidia,pins = "owc", "spdi", "spdo", "uac";
|
|
nvidia,function = "rsvd2";
|
|
};
|
|
pmc {
|
|
nvidia,pins = "pmc";
|
|
nvidia,function = "pwr_on";
|
|
};
|
|
rm {
|
|
nvidia,pins = "rm";
|
|
nvidia,function = "i2c1";
|
|
};
|
|
sdb {
|
|
nvidia,pins = "sdb", "sdc", "sdd";
|
|
nvidia,function = "pwm";
|
|
};
|
|
sdio1 {
|
|
nvidia,pins = "sdio1";
|
|
nvidia,function = "sdio1";
|
|
};
|
|
slxc {
|
|
nvidia,pins = "slxc", "slxd";
|
|
nvidia,function = "spdif";
|
|
};
|
|
spid {
|
|
nvidia,pins = "spid", "spie", "spif";
|
|
nvidia,function = "spi1";
|
|
};
|
|
spig {
|
|
nvidia,pins = "spig", "spih";
|
|
nvidia,function = "spi2_alt";
|
|
};
|
|
uaa {
|
|
nvidia,pins = "uaa", "uab", "uda";
|
|
nvidia,function = "ulpi";
|
|
};
|
|
uad {
|
|
nvidia,pins = "uad";
|
|
nvidia,function = "irda";
|
|
};
|
|
uca {
|
|
nvidia,pins = "uca", "ucb";
|
|
nvidia,function = "uartc";
|
|
};
|
|
conf_ata {
|
|
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
|
|
"cdev1", "cdev2", "dap1", "dtb", "gma",
|
|
"gmb", "gmc", "gmd", "gme", "gpu7",
|
|
"gpv", "i2cp", "pta", "rm", "slxa",
|
|
"slxk", "spia", "spib", "uac";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
conf_ck32 {
|
|
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
|
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
};
|
|
conf_csus {
|
|
nvidia,pins = "csus", "spid", "spif";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
conf_crtp {
|
|
nvidia,pins = "crtp", "dap2", "dap3", "dap4",
|
|
"dtc", "dte", "dtf", "gpu", "sdio1",
|
|
"slxc", "slxd", "spdi", "spdo", "spig",
|
|
"uda";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
conf_ddc {
|
|
nvidia,pins = "ddc", "dta", "dtd", "kbca",
|
|
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
|
"sdc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
conf_hdint {
|
|
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
|
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
|
"lvp0", "owc", "sdb";
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
conf_irrx {
|
|
nvidia,pins = "irrx", "irtx", "sdd", "spic",
|
|
"spie", "spih", "uaa", "uab", "uad",
|
|
"uca", "ucb";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
conf_lc {
|
|
nvidia,pins = "lc", "ls";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
};
|
|
conf_ld0 {
|
|
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
|
"ld5", "ld6", "ld7", "ld8", "ld9",
|
|
"ld10", "ld11", "ld12", "ld13", "ld14",
|
|
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
|
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
|
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
|
"lvs", "pmc";
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
conf_ld17_0 {
|
|
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
|
"ld23_22";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
};
|
|
};
|
|
|
|
state_i2cmux_ddc: pinmux_i2cmux_ddc {
|
|
ddc {
|
|
nvidia,pins = "ddc";
|
|
nvidia,function = "i2c2";
|
|
};
|
|
pta {
|
|
nvidia,pins = "pta";
|
|
nvidia,function = "rsvd4";
|
|
};
|
|
};
|
|
|
|
state_i2cmux_pta: pinmux_i2cmux_pta {
|
|
ddc {
|
|
nvidia,pins = "ddc";
|
|
nvidia,function = "rsvd4";
|
|
};
|
|
pta {
|
|
nvidia,pins = "pta";
|
|
nvidia,function = "i2c2";
|
|
};
|
|
};
|
|
|
|
state_i2cmux_idle: pinmux_i2cmux_idle {
|
|
ddc {
|
|
nvidia,pins = "ddc";
|
|
nvidia,function = "rsvd4";
|
|
};
|
|
pta {
|
|
nvidia,pins = "pta";
|
|
nvidia,function = "rsvd4";
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s@70002800 {
|
|
status = "okay";
|
|
};
|
|
|
|
serial@70006300 {
|
|
status = "okay";
|
|
};
|
|
|
|
i2c@7000c000 {
|
|
clock-frequency = <400000>;
|
|
status = "okay";
|
|
};
|
|
|
|
i2c@7000c400 {
|
|
clock-frequency = <100000>;
|
|
status = "okay";
|
|
};
|
|
|
|
i2cmux {
|
|
compatible = "i2c-mux-pinctrl";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
i2c-parent = <&{/i2c@7000c400}>;
|
|
|
|
pinctrl-names = "ddc", "pta", "idle";
|
|
pinctrl-0 = <&state_i2cmux_ddc>;
|
|
pinctrl-1 = <&state_i2cmux_pta>;
|
|
pinctrl-2 = <&state_i2cmux_idle>;
|
|
|
|
hdmi_ddc: i2c@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c@1 {
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
i2c@7000d000 {
|
|
clock-frequency = <400000>;
|
|
status = "okay";
|
|
|
|
pmic: tps6586x@34 {
|
|
compatible = "ti,tps6586x";
|
|
reg = <0x34>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
ti,system-power-controller;
|
|
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
|
|
/* vdd_5v0_reg must be provided by the base board */
|
|
sys-supply = <&vdd_5v0_reg>;
|
|
vin-sm0-supply = <&sys_reg>;
|
|
vin-sm1-supply = <&sys_reg>;
|
|
vin-sm2-supply = <&sys_reg>;
|
|
vinldo01-supply = <&sm2_reg>;
|
|
vinldo23-supply = <&sm2_reg>;
|
|
vinldo4-supply = <&sm2_reg>;
|
|
vinldo678-supply = <&sm2_reg>;
|
|
vinldo9-supply = <&sm2_reg>;
|
|
|
|
regulators {
|
|
sys_reg: sys {
|
|
regulator-name = "vdd_sys";
|
|
regulator-always-on;
|
|
};
|
|
|
|
sm0 {
|
|
regulator-name = "vdd_sys_sm0,vdd_core";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
sm1 {
|
|
regulator-name = "vdd_sys_sm1,vdd_cpu";
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
sm2_reg: sm2 {
|
|
regulator-name = "vdd_sys_sm2,vin_ldo*";
|
|
regulator-min-microvolt = <3700000>;
|
|
regulator-max-microvolt = <3700000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
pci_clk_reg: ldo0 {
|
|
regulator-name = "vdd_ldo0,vddio_pex_clk";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
|
|
ldo1 {
|
|
regulator-name = "vdd_ldo1,avdd_pll*";
|
|
regulator-min-microvolt = <1100000>;
|
|
regulator-max-microvolt = <1100000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo2 {
|
|
regulator-name = "vdd_ldo2,vdd_rtc";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
};
|
|
|
|
ldo3 {
|
|
regulator-name = "vdd_ldo3,avdd_usb*";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo4 {
|
|
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo5 {
|
|
regulator-name = "vdd_ldo5,vcore_mmc";
|
|
regulator-min-microvolt = <2850000>;
|
|
regulator-max-microvolt = <2850000>;
|
|
};
|
|
|
|
ldo6 {
|
|
regulator-name = "vdd_ldo6,avdd_vdac";
|
|
/*
|
|
* According to the Tegra 2 Automotive
|
|
* DataSheet, a typical value for this
|
|
* would be 2.8V, but the PMIC only
|
|
* supports 2.85V.
|
|
*/
|
|
regulator-min-microvolt = <2850000>;
|
|
regulator-max-microvolt = <2850000>;
|
|
};
|
|
|
|
hdmi_vdd_reg: ldo7 {
|
|
regulator-name = "vdd_ldo7,avdd_hdmi";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
|
|
hdmi_pll_reg: ldo8 {
|
|
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo9 {
|
|
regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
|
|
/*
|
|
* According to the Tegra 2 Automotive
|
|
* DataSheet, a typical value for this
|
|
* would be 2.8V, but the PMIC only
|
|
* supports 2.85V.
|
|
*/
|
|
regulator-min-microvolt = <2850000>;
|
|
regulator-max-microvolt = <2850000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo_rtc {
|
|
regulator-name = "vdd_rtc_out";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
|
|
temperature-sensor@4c {
|
|
compatible = "onnn,nct1008";
|
|
reg = <0x4c>;
|
|
};
|
|
};
|
|
|
|
pmc@7000e400 {
|
|
nvidia,invert-interrupt;
|
|
nvidia,suspend-mode = <1>;
|
|
nvidia,cpu-pwr-good-time = <5000>;
|
|
nvidia,cpu-pwr-off-time = <5000>;
|
|
nvidia,core-pwr-good-time = <3845 3845>;
|
|
nvidia,core-pwr-off-time = <3875>;
|
|
nvidia,sys-clock-req-active-high;
|
|
};
|
|
|
|
pcie-controller@80003000 {
|
|
avdd-pex-supply = <&pci_vdd_reg>;
|
|
vdd-pex-supply = <&pci_vdd_reg>;
|
|
avdd-pex-pll-supply = <&pci_vdd_reg>;
|
|
avdd-plle-supply = <&pci_vdd_reg>;
|
|
vddio-pex-clk-supply = <&pci_clk_reg>;
|
|
};
|
|
|
|
usb@c5008000 {
|
|
status = "okay";
|
|
};
|
|
|
|
usb-phy@c5008000 {
|
|
status = "okay";
|
|
};
|
|
|
|
sdhci@c8000600 {
|
|
cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
|
|
wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
|
|
bus-width = <4>;
|
|
status = "okay";
|
|
};
|
|
|
|
clocks {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
clk32k_in: clock@0 {
|
|
compatible = "fixed-clock";
|
|
reg=<0>;
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
};
|
|
|
|
regulators {
|
|
compatible = "simple-bus";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pci_vdd_reg: regulator@1 {
|
|
compatible = "regulator-fixed";
|
|
reg = <1>;
|
|
regulator-name = "vdd_1v05";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
gpio = <&pmic 2 0>;
|
|
enable-active-high;
|
|
};
|
|
};
|
|
};
|