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c556d98903
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
534 lines
13 KiB
C
534 lines
13 KiB
C
/*
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* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
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* Copyright 2005 Stephane Marchesin
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*
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* The Weather Channel (TM) funded Tungsten Graphics to develop the
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* initial release of the Radeon 8500 driver under the XFree86 license.
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* This notice must be preserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "drm_sarea.h"
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#include "nouveau_drv.h"
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/*
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* NV10-NV40 tiling helpers
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*/
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static void
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nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
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uint32_t size, uint32_t pitch)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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tile->addr = addr;
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tile->size = size;
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tile->used = !!pitch;
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nouveau_fence_unref((void **)&tile->fence);
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if (!pfifo->cache_flush(dev))
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return;
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pfifo->reassign(dev, false);
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pfifo->cache_flush(dev);
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pfifo->cache_pull(dev, false);
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nouveau_wait_for_idle(dev);
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pgraph->set_region_tiling(dev, i, addr, size, pitch);
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pfb->set_region_tiling(dev, i, addr, size, pitch);
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pfifo->cache_pull(dev, true);
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pfifo->reassign(dev, true);
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}
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struct nouveau_tile_reg *
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nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
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uint32_t pitch)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
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int i;
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spin_lock(&dev_priv->tile.lock);
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for (i = 0; i < pfb->num_tiles; i++) {
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if (tile[i].used)
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/* Tile region in use. */
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continue;
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if (tile[i].fence &&
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!nouveau_fence_signalled(tile[i].fence, NULL))
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/* Pending tile region. */
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continue;
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if (max(tile[i].addr, addr) <
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min(tile[i].addr + tile[i].size, addr + size))
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/* Kill an intersecting tile region. */
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nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
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if (pitch && !found) {
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/* Free tile region. */
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nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
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found = &tile[i];
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}
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}
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spin_unlock(&dev_priv->tile.lock);
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return found;
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}
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void
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nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
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struct nouveau_fence *fence)
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{
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if (fence) {
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/* Mark it as pending. */
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tile->fence = fence;
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nouveau_fence_ref(fence);
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}
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tile->used = false;
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}
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/*
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* NV50 VM helpers
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*/
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int
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nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
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uint32_t flags, uint64_t phys)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *pgt;
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unsigned block;
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int i;
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virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
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size = (size >> 16) << 1;
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phys |= ((uint64_t)flags << 32);
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phys |= 1;
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if (dev_priv->vram_sys_base) {
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phys += dev_priv->vram_sys_base;
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phys |= 0x30;
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}
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while (size) {
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unsigned offset_h = upper_32_bits(phys);
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unsigned offset_l = lower_32_bits(phys);
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unsigned pte, end;
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for (i = 7; i >= 0; i--) {
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block = 1 << (i + 1);
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if (size >= block && !(virt & (block - 1)))
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break;
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}
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offset_l |= (i << 7);
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phys += block << 15;
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size -= block;
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while (block) {
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pgt = dev_priv->vm_vram_pt[virt >> 14];
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pte = virt & 0x3ffe;
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end = pte + block;
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if (end > 16384)
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end = 16384;
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block -= (end - pte);
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virt += (end - pte);
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while (pte < end) {
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nv_wo32(dev, pgt, pte++, offset_l);
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nv_wo32(dev, pgt, pte++, offset_h);
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}
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}
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}
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dev_priv->engine.instmem.flush(dev);
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nv50_vm_flush(dev, 5);
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nv50_vm_flush(dev, 0);
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nv50_vm_flush(dev, 4);
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nv50_vm_flush(dev, 6);
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return 0;
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}
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void
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nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *pgt;
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unsigned pages, pte, end;
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virt -= dev_priv->vm_vram_base;
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pages = (size >> 16) << 1;
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while (pages) {
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pgt = dev_priv->vm_vram_pt[virt >> 29];
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pte = (virt & 0x1ffe0000ULL) >> 15;
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end = pte + pages;
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if (end > 16384)
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end = 16384;
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pages -= (end - pte);
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virt += (end - pte) << 15;
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while (pte < end)
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nv_wo32(dev, pgt, pte++, 0);
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}
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dev_priv->engine.instmem.flush(dev);
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nv50_vm_flush(dev, 5);
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nv50_vm_flush(dev, 0);
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nv50_vm_flush(dev, 4);
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nv50_vm_flush(dev, 6);
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}
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/*
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* Cleanup everything
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*/
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void
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nouveau_mem_close(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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nouveau_bo_unpin(dev_priv->vga_ram);
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nouveau_bo_ref(NULL, &dev_priv->vga_ram);
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ttm_bo_device_release(&dev_priv->ttm.bdev);
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nouveau_ttm_global_release(dev_priv);
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if (drm_core_has_AGP(dev) && dev->agp) {
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struct drm_agp_mem *entry, *tempe;
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/* Remove AGP resources, but leave dev->agp
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intact until drv_cleanup is called. */
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list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
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if (entry->bound)
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drm_unbind_agp(entry->memory);
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drm_free_agp(entry->memory, entry->pages);
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kfree(entry);
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}
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INIT_LIST_HEAD(&dev->agp->memory);
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if (dev->agp->acquired)
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drm_agp_release(dev);
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dev->agp->acquired = 0;
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dev->agp->enabled = 0;
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}
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if (dev_priv->fb_mtrr) {
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drm_mtrr_del(dev_priv->fb_mtrr,
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pci_resource_start(dev->pdev, 1),
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pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
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dev_priv->fb_mtrr = -1;
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}
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}
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static uint32_t
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nouveau_mem_detect_nv04(struct drm_device *dev)
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{
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uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
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if (boot0 & 0x00000100)
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return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
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switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
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case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
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return 32 * 1024 * 1024;
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case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
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return 16 * 1024 * 1024;
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case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
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return 8 * 1024 * 1024;
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case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
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return 4 * 1024 * 1024;
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}
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return 0;
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}
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static uint32_t
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nouveau_mem_detect_nforce(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct pci_dev *bridge;
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uint32_t mem;
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bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
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if (!bridge) {
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NV_ERROR(dev, "no bridge device\n");
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return 0;
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}
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if (dev_priv->flags & NV_NFORCE) {
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pci_read_config_dword(bridge, 0x7C, &mem);
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return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
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} else
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if (dev_priv->flags & NV_NFORCE2) {
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pci_read_config_dword(bridge, 0x84, &mem);
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return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
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}
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NV_ERROR(dev, "impossible!\n");
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return 0;
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}
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/* returns the amount of FB ram in bytes */
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int
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nouveau_mem_detect(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (dev_priv->card_type == NV_04) {
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dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
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} else
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if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
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dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
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} else
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if (dev_priv->card_type < NV_50) {
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dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
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dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
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} else
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if (dev_priv->card_type < NV_C0) {
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dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
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dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
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dev_priv->vram_size &= 0xffffffff00ll;
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if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) {
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dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
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dev_priv->vram_sys_base <<= 12;
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}
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} else {
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dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20;
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dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
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}
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NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
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if (dev_priv->vram_sys_base) {
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NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
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dev_priv->vram_sys_base);
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}
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if (dev_priv->vram_size)
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return 0;
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return -ENOMEM;
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}
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int
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nouveau_mem_reset_agp(struct drm_device *dev)
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{
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#if __OS_HAS_AGP
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uint32_t saved_pci_nv_1, pmc_enable;
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int ret;
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/* First of all, disable fast writes, otherwise if it's
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* already enabled in the AGP bridge and we disable the card's
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* AGP controller we might be locking ourselves out of it. */
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if (nv_rd32(dev, NV04_PBUS_PCI_NV_19) & PCI_AGP_COMMAND_FW) {
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struct drm_agp_info info;
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struct drm_agp_mode mode;
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ret = drm_agp_info(dev, &info);
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if (ret)
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return ret;
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mode.mode = info.mode & ~PCI_AGP_COMMAND_FW;
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ret = drm_agp_enable(dev, mode);
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if (ret)
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return ret;
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}
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saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
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/* clear busmaster bit */
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nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
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/* disable AGP */
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nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
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/* power cycle pgraph, if enabled */
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pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
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if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
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nv_wr32(dev, NV03_PMC_ENABLE,
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pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
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NV_PMC_ENABLE_PGRAPH);
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}
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/* and restore (gives effect of resetting AGP) */
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nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
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#endif
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return 0;
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}
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int
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nouveau_mem_init_agp(struct drm_device *dev)
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{
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#if __OS_HAS_AGP
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_agp_info info;
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struct drm_agp_mode mode;
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int ret;
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if (!dev->agp->acquired) {
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ret = drm_agp_acquire(dev);
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if (ret) {
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NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
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return ret;
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}
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}
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nouveau_mem_reset_agp(dev);
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ret = drm_agp_info(dev, &info);
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if (ret) {
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NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
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return ret;
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}
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/* see agp.h for the AGPSTAT_* modes available */
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mode.mode = info.mode;
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ret = drm_agp_enable(dev, mode);
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if (ret) {
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NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
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return ret;
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}
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dev_priv->gart_info.type = NOUVEAU_GART_AGP;
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dev_priv->gart_info.aper_base = info.aperture_base;
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dev_priv->gart_info.aper_size = info.aperture_size;
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#endif
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return 0;
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}
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int
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nouveau_mem_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
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int ret, dma_bits = 32;
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dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
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dev_priv->gart_info.type = NOUVEAU_GART_NONE;
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if (dev_priv->card_type >= NV_50 &&
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pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
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dma_bits = 40;
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ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
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if (ret) {
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NV_ERROR(dev, "Error setting DMA mask: %d\n", ret);
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return ret;
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}
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ret = nouveau_ttm_global_init(dev_priv);
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if (ret)
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return ret;
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ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
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dev_priv->ttm.bo_global_ref.ref.object,
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&nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
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dma_bits <= 32 ? true : false);
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if (ret) {
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NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
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return ret;
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}
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spin_lock_init(&dev_priv->tile.lock);
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dev_priv->fb_available_size = dev_priv->vram_size;
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dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
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if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
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dev_priv->fb_mappable_pages =
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pci_resource_len(dev->pdev, 1);
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dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
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/* remove reserved space at end of vram from available amount */
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dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
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dev_priv->fb_aper_free = dev_priv->fb_available_size;
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/* mappable vram */
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ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
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dev_priv->fb_available_size >> PAGE_SHIFT);
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if (ret) {
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NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
|
|
0, 0, true, true, &dev_priv->vga_ram);
|
|
if (ret == 0)
|
|
ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
|
|
if (ret) {
|
|
NV_WARN(dev, "failed to reserve VGA memory\n");
|
|
nouveau_bo_ref(NULL, &dev_priv->vga_ram);
|
|
}
|
|
|
|
/* GART */
|
|
#if !defined(__powerpc__) && !defined(__ia64__)
|
|
if (drm_device_is_agp(dev) && dev->agp && !nouveau_noagp) {
|
|
ret = nouveau_mem_init_agp(dev);
|
|
if (ret)
|
|
NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
|
|
}
|
|
#endif
|
|
|
|
if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
|
|
ret = nouveau_sgdma_init(dev);
|
|
if (ret) {
|
|
NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
NV_INFO(dev, "%d MiB GART (aperture)\n",
|
|
(int)(dev_priv->gart_info.aper_size >> 20));
|
|
dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
|
|
|
|
ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
|
|
dev_priv->gart_info.aper_size >> PAGE_SHIFT);
|
|
if (ret) {
|
|
NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
|
|
pci_resource_len(dev->pdev, 1),
|
|
DRM_MTRR_WC);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|