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It looks like the HIP06/07 SoCs have extra bits in their GICD_TYPER registers, which confuse the GICv3.1 code (these systems appear to expose ESPIs while they actually don't). Detect these systems as early as possible and wipe the fields that should be RES0 in the register. Tested-by: John Garry <john.garry@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> |
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| .. | ||
| acpi_object_usage.rst | ||
| arm-acpi.rst | ||
| booting.rst | ||
| cpu-feature-registers.rst | ||
| elf_hwcaps.rst | ||
| hugetlbpage.rst | ||
| index.rst | ||
| legacy_instructions.rst | ||
| memory.rst | ||
| perf.txt | ||
| pointer-authentication.rst | ||
| silicon-errata.rst | ||
| sve.rst | ||
| tagged-pointers.rst | ||