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c130a7602e
Registers have moved around across TSENS generations. For example, the CTRL register was at offset 0x0 in the SROT region on msm8916 but is at offset 0x4 in newer v2 based TSENS HW blocks. Allow passing offsets of important registers so that we can continue to use common functions. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
237 lines
6.5 KiB
C
237 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#include <linux/platform_device.h>
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#include "tsens.h"
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/* eeprom layout data for 8974 */
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#define BASE1_MASK 0xff
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#define S0_P1_MASK 0x3f00
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#define S1_P1_MASK 0xfc000
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#define S2_P1_MASK 0x3f00000
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#define S3_P1_MASK 0xfc000000
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#define S4_P1_MASK 0x3f
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#define S5_P1_MASK 0xfc0
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#define S6_P1_MASK 0x3f000
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#define S7_P1_MASK 0xfc0000
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#define S8_P1_MASK 0x3f000000
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#define S8_P1_MASK_BKP 0x3f
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#define S9_P1_MASK 0x3f
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#define S9_P1_MASK_BKP 0xfc0
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#define S10_P1_MASK 0xfc0
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#define S10_P1_MASK_BKP 0x3f000
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#define CAL_SEL_0_1 0xc0000000
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#define CAL_SEL_2 0x40000000
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#define CAL_SEL_SHIFT 30
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#define CAL_SEL_SHIFT_2 28
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#define S0_P1_SHIFT 8
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#define S1_P1_SHIFT 14
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#define S2_P1_SHIFT 20
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#define S3_P1_SHIFT 26
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#define S5_P1_SHIFT 6
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#define S6_P1_SHIFT 12
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#define S7_P1_SHIFT 18
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#define S8_P1_SHIFT 24
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#define S9_P1_BKP_SHIFT 6
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#define S10_P1_SHIFT 6
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#define S10_P1_BKP_SHIFT 12
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#define BASE2_SHIFT 12
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#define BASE2_BKP_SHIFT 18
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#define S0_P2_SHIFT 20
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#define S0_P2_BKP_SHIFT 26
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#define S1_P2_SHIFT 26
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#define S2_P2_BKP_SHIFT 6
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#define S3_P2_SHIFT 6
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#define S3_P2_BKP_SHIFT 12
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#define S4_P2_SHIFT 12
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#define S4_P2_BKP_SHIFT 18
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#define S5_P2_SHIFT 18
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#define S5_P2_BKP_SHIFT 24
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#define S6_P2_SHIFT 24
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#define S7_P2_BKP_SHIFT 6
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#define S8_P2_SHIFT 6
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#define S8_P2_BKP_SHIFT 12
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#define S9_P2_SHIFT 12
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#define S9_P2_BKP_SHIFT 18
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#define S10_P2_SHIFT 18
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#define S10_P2_BKP_SHIFT 24
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#define BASE2_MASK 0xff000
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#define BASE2_BKP_MASK 0xfc0000
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#define S0_P2_MASK 0x3f00000
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#define S0_P2_BKP_MASK 0xfc000000
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#define S1_P2_MASK 0xfc000000
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#define S1_P2_BKP_MASK 0x3f
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#define S2_P2_MASK 0x3f
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#define S2_P2_BKP_MASK 0xfc0
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#define S3_P2_MASK 0xfc0
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#define S3_P2_BKP_MASK 0x3f000
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#define S4_P2_MASK 0x3f000
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#define S4_P2_BKP_MASK 0xfc0000
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#define S5_P2_MASK 0xfc0000
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#define S5_P2_BKP_MASK 0x3f000000
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#define S6_P2_MASK 0x3f000000
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#define S6_P2_BKP_MASK 0x3f
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#define S7_P2_MASK 0x3f
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#define S7_P2_BKP_MASK 0xfc0
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#define S8_P2_MASK 0xfc0
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#define S8_P2_BKP_MASK 0x3f000
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#define S9_P2_MASK 0x3f000
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#define S9_P2_BKP_MASK 0xfc0000
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#define S10_P2_MASK 0xfc0000
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#define S10_P2_BKP_MASK 0x3f000000
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#define BKP_SEL 0x3
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#define BKP_REDUN_SEL 0xe0000000
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#define BKP_REDUN_SHIFT 29
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#define BIT_APPEND 0x3
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static int calibrate_8974(struct tsens_device *tmdev)
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{
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int base1 = 0, base2 = 0, i;
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u32 p1[11], p2[11];
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int mode = 0;
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u32 *calib, *bkp;
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u32 calib_redun_sel;
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calib = (u32 *)qfprom_read(tmdev->dev, "calib");
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if (IS_ERR(calib))
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return PTR_ERR(calib);
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bkp = (u32 *)qfprom_read(tmdev->dev, "calib_backup");
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if (IS_ERR(bkp))
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return PTR_ERR(bkp);
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calib_redun_sel = bkp[1] & BKP_REDUN_SEL;
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calib_redun_sel >>= BKP_REDUN_SHIFT;
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if (calib_redun_sel == BKP_SEL) {
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mode = (calib[4] & CAL_SEL_0_1) >> CAL_SEL_SHIFT;
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mode |= (calib[5] & CAL_SEL_2) >> CAL_SEL_SHIFT_2;
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switch (mode) {
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case TWO_PT_CALIB:
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base2 = (bkp[2] & BASE2_BKP_MASK) >> BASE2_BKP_SHIFT;
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p2[0] = (bkp[2] & S0_P2_BKP_MASK) >> S0_P2_BKP_SHIFT;
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p2[1] = (bkp[3] & S1_P2_BKP_MASK);
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p2[2] = (bkp[3] & S2_P2_BKP_MASK) >> S2_P2_BKP_SHIFT;
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p2[3] = (bkp[3] & S3_P2_BKP_MASK) >> S3_P2_BKP_SHIFT;
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p2[4] = (bkp[3] & S4_P2_BKP_MASK) >> S4_P2_BKP_SHIFT;
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p2[5] = (calib[4] & S5_P2_BKP_MASK) >> S5_P2_BKP_SHIFT;
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p2[6] = (calib[5] & S6_P2_BKP_MASK);
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p2[7] = (calib[5] & S7_P2_BKP_MASK) >> S7_P2_BKP_SHIFT;
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p2[8] = (calib[5] & S8_P2_BKP_MASK) >> S8_P2_BKP_SHIFT;
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p2[9] = (calib[5] & S9_P2_BKP_MASK) >> S9_P2_BKP_SHIFT;
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p2[10] = (calib[5] & S10_P2_BKP_MASK) >> S10_P2_BKP_SHIFT;
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/* Fall through */
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case ONE_PT_CALIB:
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case ONE_PT_CALIB2:
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base1 = bkp[0] & BASE1_MASK;
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p1[0] = (bkp[0] & S0_P1_MASK) >> S0_P1_SHIFT;
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p1[1] = (bkp[0] & S1_P1_MASK) >> S1_P1_SHIFT;
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p1[2] = (bkp[0] & S2_P1_MASK) >> S2_P1_SHIFT;
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p1[3] = (bkp[0] & S3_P1_MASK) >> S3_P1_SHIFT;
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p1[4] = (bkp[1] & S4_P1_MASK);
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p1[5] = (bkp[1] & S5_P1_MASK) >> S5_P1_SHIFT;
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p1[6] = (bkp[1] & S6_P1_MASK) >> S6_P1_SHIFT;
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p1[7] = (bkp[1] & S7_P1_MASK) >> S7_P1_SHIFT;
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p1[8] = (bkp[2] & S8_P1_MASK_BKP) >> S8_P1_SHIFT;
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p1[9] = (bkp[2] & S9_P1_MASK_BKP) >> S9_P1_BKP_SHIFT;
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p1[10] = (bkp[2] & S10_P1_MASK_BKP) >> S10_P1_BKP_SHIFT;
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break;
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}
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} else {
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mode = (calib[1] & CAL_SEL_0_1) >> CAL_SEL_SHIFT;
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mode |= (calib[3] & CAL_SEL_2) >> CAL_SEL_SHIFT_2;
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switch (mode) {
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case TWO_PT_CALIB:
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base2 = (calib[2] & BASE2_MASK) >> BASE2_SHIFT;
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p2[0] = (calib[2] & S0_P2_MASK) >> S0_P2_SHIFT;
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p2[1] = (calib[2] & S1_P2_MASK) >> S1_P2_SHIFT;
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p2[2] = (calib[3] & S2_P2_MASK);
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p2[3] = (calib[3] & S3_P2_MASK) >> S3_P2_SHIFT;
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p2[4] = (calib[3] & S4_P2_MASK) >> S4_P2_SHIFT;
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p2[5] = (calib[3] & S5_P2_MASK) >> S5_P2_SHIFT;
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p2[6] = (calib[3] & S6_P2_MASK) >> S6_P2_SHIFT;
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p2[7] = (calib[4] & S7_P2_MASK);
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p2[8] = (calib[4] & S8_P2_MASK) >> S8_P2_SHIFT;
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p2[9] = (calib[4] & S9_P2_MASK) >> S9_P2_SHIFT;
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p2[10] = (calib[4] & S10_P2_MASK) >> S10_P2_SHIFT;
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/* Fall through */
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case ONE_PT_CALIB:
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case ONE_PT_CALIB2:
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base1 = calib[0] & BASE1_MASK;
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p1[0] = (calib[0] & S0_P1_MASK) >> S0_P1_SHIFT;
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p1[1] = (calib[0] & S1_P1_MASK) >> S1_P1_SHIFT;
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p1[2] = (calib[0] & S2_P1_MASK) >> S2_P1_SHIFT;
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p1[3] = (calib[0] & S3_P1_MASK) >> S3_P1_SHIFT;
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p1[4] = (calib[1] & S4_P1_MASK);
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p1[5] = (calib[1] & S5_P1_MASK) >> S5_P1_SHIFT;
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p1[6] = (calib[1] & S6_P1_MASK) >> S6_P1_SHIFT;
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p1[7] = (calib[1] & S7_P1_MASK) >> S7_P1_SHIFT;
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p1[8] = (calib[1] & S8_P1_MASK) >> S8_P1_SHIFT;
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p1[9] = (calib[2] & S9_P1_MASK);
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p1[10] = (calib[2] & S10_P1_MASK) >> S10_P1_SHIFT;
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break;
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}
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}
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switch (mode) {
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case ONE_PT_CALIB:
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for (i = 0; i < tmdev->num_sensors; i++)
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p1[i] += (base1 << 2) | BIT_APPEND;
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break;
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case TWO_PT_CALIB:
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for (i = 0; i < tmdev->num_sensors; i++) {
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p2[i] += base2;
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p2[i] <<= 2;
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p2[i] |= BIT_APPEND;
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}
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/* Fall through */
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case ONE_PT_CALIB2:
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for (i = 0; i < tmdev->num_sensors; i++) {
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p1[i] += base1;
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p1[i] <<= 2;
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p1[i] |= BIT_APPEND;
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}
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break;
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default:
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for (i = 0; i < tmdev->num_sensors; i++)
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p2[i] = 780;
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p1[0] = 502;
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p1[1] = 509;
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p1[2] = 503;
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p1[3] = 509;
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p1[4] = 505;
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p1[5] = 509;
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p1[6] = 507;
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p1[7] = 510;
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p1[8] = 508;
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p1[9] = 509;
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p1[10] = 508;
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break;
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}
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compute_intercept_slope(tmdev, p1, p2, mode);
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return 0;
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}
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static const struct tsens_ops ops_8974 = {
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.init = init_common,
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.calibrate = calibrate_8974,
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.get_temp = get_temp_common,
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};
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const struct tsens_data data_8974 = {
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.num_sensors = 11,
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.ops = &ops_8974,
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.reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 },
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};
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