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7051924f77
This driver has been functional and stable throughout the year it has spent in the staging area. It has been patched for minor bugs, coding style issues and improvements during this period. This is the second submission of this move-out, after making several style improvements, as suggested by Dan Carpenter. Signed-off-by: Eli Billauer <eli.billauer@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
161 lines
3.7 KiB
C
161 lines
3.7 KiB
C
/*
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* linux/drivers/misc/xillybus.h
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*
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* Copyright 2011 Xillybus Ltd, http://xillybus.com
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*
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* Header file for the Xillybus FPGA/host framework.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the smems of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __XILLYBUS_H
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#define __XILLYBUS_H
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#include <linux/list.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/cdev.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/workqueue.h>
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struct xilly_endpoint_hardware;
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struct xilly_buffer {
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void *addr;
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dma_addr_t dma_addr;
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int end_offset; /* Counting elements, not bytes */
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};
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struct xilly_idt_handle {
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unsigned char *chandesc;
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unsigned char *idt;
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int entries;
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};
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/*
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* Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so
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* wr_* buffers are those consumed by read(), since the FPGA writes to them
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* and vice versa.
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*/
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struct xilly_channel {
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struct xilly_endpoint *endpoint;
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int chan_num;
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int log2_element_size;
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int seekable;
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struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
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int num_wr_buffers;
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unsigned int wr_buf_size; /* In bytes */
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int wr_fpga_buf_idx;
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int wr_host_buf_idx;
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int wr_host_buf_pos;
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int wr_empty;
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int wr_ready; /* Significant only when wr_empty == 1 */
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int wr_sleepy;
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int wr_eof;
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int wr_hangup;
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spinlock_t wr_spinlock;
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struct mutex wr_mutex;
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wait_queue_head_t wr_wait;
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wait_queue_head_t wr_ready_wait;
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int wr_ref_count;
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int wr_synchronous;
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int wr_allow_partial;
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int wr_exclusive_open;
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int wr_supports_nonempty;
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struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
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int num_rd_buffers;
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unsigned int rd_buf_size; /* In bytes */
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int rd_fpga_buf_idx;
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int rd_host_buf_pos;
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int rd_host_buf_idx;
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int rd_full;
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spinlock_t rd_spinlock;
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struct mutex rd_mutex;
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wait_queue_head_t rd_wait;
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int rd_ref_count;
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int rd_allow_partial;
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int rd_synchronous;
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int rd_exclusive_open;
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struct delayed_work rd_workitem;
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unsigned char rd_leftovers[4];
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};
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struct xilly_endpoint {
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/*
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* One of pdev and dev is always NULL, and the other is a valid
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* pointer, depending on the type of device
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*/
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struct pci_dev *pdev;
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struct device *dev;
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struct xilly_endpoint_hardware *ephw;
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struct list_head ep_list;
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int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
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__iomem void *registers;
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int fatal_error;
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struct mutex register_mutex;
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wait_queue_head_t ep_wait;
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/* Channels and message handling */
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struct cdev cdev;
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int major;
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int lowest_minor; /* Highest minor = lowest_minor + num_channels - 1 */
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int num_channels; /* EXCLUDING message buffer */
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struct xilly_channel **channels;
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int msg_counter;
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int failed_messages;
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int idtlen;
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u32 *msgbuf_addr;
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dma_addr_t msgbuf_dma_addr;
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unsigned int msg_buf_size;
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};
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struct xilly_endpoint_hardware {
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struct module *owner;
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void (*hw_sync_sgl_for_cpu)(struct xilly_endpoint *,
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dma_addr_t,
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size_t,
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int);
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void (*hw_sync_sgl_for_device)(struct xilly_endpoint *,
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dma_addr_t,
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size_t,
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int);
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int (*map_single)(struct xilly_endpoint *,
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void *,
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size_t,
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int,
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dma_addr_t *);
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};
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struct xilly_mapping {
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void *device;
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dma_addr_t dma_addr;
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size_t size;
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int direction;
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};
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irqreturn_t xillybus_isr(int irq, void *data);
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struct xilly_endpoint *xillybus_init_endpoint(struct pci_dev *pdev,
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struct device *dev,
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struct xilly_endpoint_hardware
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*ephw);
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int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint);
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void xillybus_endpoint_remove(struct xilly_endpoint *endpoint);
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#endif /* __XILLYBUS_H */
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