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Add mt8186 platform and affiliated driver. Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220718162204.26238-3-jiaxin.yu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
107 lines
2.5 KiB
C
107 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* mt8186-afe-clk.h -- Mediatek 8186 afe clock ctrl definition
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*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
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*/
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#ifndef _MT8186_AFE_CLOCK_CTRL_H_
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#define _MT8186_AFE_CLOCK_CTRL_H_
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#define PERI_BUS_DCM_CTRL 0x74
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/* APLL */
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#define APLL1_W_NAME "APLL1"
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#define APLL2_W_NAME "APLL2"
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enum {
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MT8186_APLL1 = 0,
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MT8186_APLL2,
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};
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enum {
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CLK_AFE = 0,
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CLK_DAC,
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CLK_DAC_PREDIS,
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CLK_ADC,
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CLK_TML,
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CLK_APLL22M,
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CLK_APLL24M,
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CLK_APLL1_TUNER,
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CLK_APLL2_TUNER,
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CLK_TDM,
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CLK_NLE,
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CLK_DAC_HIRES,
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CLK_ADC_HIRES,
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CLK_I2S1_BCLK,
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CLK_I2S2_BCLK,
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CLK_I2S3_BCLK,
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CLK_I2S4_BCLK,
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CLK_CONNSYS_I2S_ASRC,
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CLK_GENERAL1_ASRC,
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CLK_GENERAL2_ASRC,
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CLK_ADC_HIRES_TML,
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CLK_ADDA6_ADC,
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CLK_ADDA6_ADC_HIRES,
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CLK_3RD_DAC,
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CLK_3RD_DAC_PREDIS,
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CLK_3RD_DAC_TML,
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CLK_3RD_DAC_HIRES,
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CLK_ETDM_IN1_BCLK,
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CLK_ETDM_OUT1_BCLK,
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CLK_INFRA_SYS_AUDIO,
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CLK_INFRA_AUDIO_26M,
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CLK_MUX_AUDIO,
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CLK_MUX_AUDIOINTBUS,
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CLK_TOP_MAINPLL_D2_D4,
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/* apll related mux */
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CLK_TOP_MUX_AUD_1,
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CLK_TOP_APLL1_CK,
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CLK_TOP_MUX_AUD_2,
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CLK_TOP_APLL2_CK,
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CLK_TOP_MUX_AUD_ENG1,
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CLK_TOP_APLL1_D8,
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CLK_TOP_MUX_AUD_ENG2,
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CLK_TOP_APLL2_D8,
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CLK_TOP_MUX_AUDIO_H,
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CLK_TOP_I2S0_M_SEL,
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CLK_TOP_I2S1_M_SEL,
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CLK_TOP_I2S2_M_SEL,
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CLK_TOP_I2S4_M_SEL,
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CLK_TOP_TDM_M_SEL,
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CLK_TOP_APLL12_DIV0,
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CLK_TOP_APLL12_DIV1,
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CLK_TOP_APLL12_DIV2,
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CLK_TOP_APLL12_DIV4,
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CLK_TOP_APLL12_DIV_TDM,
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CLK_CLK26M,
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CLK_NUM
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};
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struct mtk_base_afe;
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int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe, int clk_id);
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int mt8186_init_clock(struct mtk_base_afe *afe);
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void mt8186_deinit_clock(void *priv);
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int mt8186_afe_enable_cgs(struct mtk_base_afe *afe);
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void mt8186_afe_disable_cgs(struct mtk_base_afe *afe);
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int mt8186_afe_enable_clock(struct mtk_base_afe *afe);
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void mt8186_afe_disable_clock(struct mtk_base_afe *afe);
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int mt8186_afe_suspend_clock(struct mtk_base_afe *afe);
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int mt8186_afe_resume_clock(struct mtk_base_afe *afe);
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int mt8186_apll1_enable(struct mtk_base_afe *afe);
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void mt8186_apll1_disable(struct mtk_base_afe *afe);
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int mt8186_apll2_enable(struct mtk_base_afe *afe);
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void mt8186_apll2_disable(struct mtk_base_afe *afe);
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int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll);
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int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
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int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
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/* these will be replaced by using CCF */
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int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
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void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id);
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#endif
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