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9598566721
The device tree binding models Tegra30 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: fixed typo in binding doc] Signed-off-by: Stephen Warren <swarren@nvidia.com>
263 lines
4.4 KiB
Plaintext
263 lines
4.4 KiB
Plaintext
NVIDIA Tegra30 Clock And Reset Controller
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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for muxing and gating Tegra's clocks, and setting their rates.
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Required properties :
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- compatible : Should be "nvidia,tegra30-car"
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- reg : Should contain CAR registers location and length
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- clocks : Should contain phandle and clock specifiers for two clocks:
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the 32 KHz "32k_in", and the board-specific oscillator "osc".
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- #clock-cells : Should be 1.
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In clock consumers, this cell represents the clock ID exposed by the CAR.
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The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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registers. These IDs often match those in the CAR's RST_DEVICES registers,
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but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
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this case, those clocks are assigned IDs above 160 in order to highlight
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this issue. Implementations that interpret these clock IDs as bit values
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within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
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explicitly handle these special cases.
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The balance of the clocks controlled by the CAR are assigned IDs of 160 and
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above.
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0 cpu
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1 unassigned
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2 unassigned
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3 unassigned
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4 rtc
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5 timer
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6 uarta
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7 unassigned (register bit affects uartb and vfir)
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8 gpio
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9 sdmmc2
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10 unassigned (register bit affects spdif_in and spdif_out)
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11 i2s1
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12 i2c1
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13 ndflash
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14 sdmmc1
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15 sdmmc4
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16 unassigned
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17 pwm
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18 i2s2
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19 epp
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20 unassigned (register bit affects vi and vi_sensor)
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21 2d
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22 usbd
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23 isp
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24 3d
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25 unassigned
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26 disp2
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27 disp1
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28 host1x
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29 vcp
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30 i2s0
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31 cop_cache
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32 mc
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33 ahbdma
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34 apbdma
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35 unassigned
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36 kbc
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37 statmon
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38 pmc
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39 unassigned (register bit affects fuse and fuse_burn)
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40 kfuse
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41 sbc1
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42 nor
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43 unassigned
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44 sbc2
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45 unassigned
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46 sbc3
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47 i2c5
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48 dsia
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49 unassigned (register bit affects cve and tvo)
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50 mipi
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51 hdmi
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52 csi
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53 tvdac
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54 i2c2
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55 uartc
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56 unassigned
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57 emc
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58 usb2
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59 usb3
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60 mpe
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61 vde
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62 bsea
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63 bsev
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64 speedo
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65 uartd
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66 uarte
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67 i2c3
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68 sbc4
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69 sdmmc3
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70 pcie
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71 owr
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72 afi
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73 csite
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74 pciex
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75 avpucq
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76 la
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77 unassigned
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78 unassigned
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79 dtv
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80 ndspeed
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81 i2cslow
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82 dsib
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83 unassigned
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84 irama
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85 iramb
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86 iramc
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87 iramd
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88 cram2
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89 unassigned
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90 audio_2x a/k/a audio_2x_sync_clk
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91 unassigned
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92 csus
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93 cdev2
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94 cdev1
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95 unassigned
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96 cpu_g
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97 cpu_lp
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98 3d2
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99 mselect
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100 tsensor
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101 i2s3
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102 i2s4
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103 i2c4
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104 sbc5
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105 sbc6
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106 d_audio
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107 apbif
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108 dam0
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109 dam1
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110 dam2
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111 hda2codec_2x
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112 atomics
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113 audio0_2x
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114 audio1_2x
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115 audio2_2x
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116 audio3_2x
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117 audio4_2x
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118 audio5_2x
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119 actmon
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120 extern1
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121 extern2
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122 extern3
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123 sata_oob
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124 sata
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125 hda
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127 se
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128 hda2hdmi
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129 sata_cold
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160 uartb
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161 vfir
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162 spdif_in
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163 spdif_out
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164 vi
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165 vi_sensor
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166 fuse
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167 fuse_burn
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168 cve
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169 tvo
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170 clk_32k
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171 clk_m
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172 clk_m_div2
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173 clk_m_div4
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174 pll_ref
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175 pll_c
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176 pll_c_out1
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177 pll_m
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178 pll_m_out1
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179 pll_p
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180 pll_p_out1
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181 pll_p_out2
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182 pll_p_out3
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183 pll_p_out4
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184 pll_a
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185 pll_a_out0
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186 pll_d
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187 pll_d_out0
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188 pll_d2
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189 pll_d2_out0
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190 pll_u
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191 pll_x
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192 pll_x_out0
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193 pll_e
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194 spdif_in_sync
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195 i2s0_sync
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196 i2s1_sync
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197 i2s2_sync
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198 i2s3_sync
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199 i2s4_sync
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200 vimclk
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201 audio0
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202 audio1
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203 audio2
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204 audio3
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205 audio4
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206 audio5
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207 clk_out_1 (extern1)
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208 clk_out_2 (extern2)
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209 clk_out_3 (extern3)
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210 sclk
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211 blink
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212 cclk_g
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213 cclk_lp
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214 twd
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215 cml0
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216 cml1
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217 hclk
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218 pclk
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Example SoC include file:
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/ {
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tegra_car: clock {
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compatible = "nvidia,tegra30-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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usb@c5004000 {
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clocks = <&tegra_car 58>; /* usb2 */
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};
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};
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Example board file:
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/ {
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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osc: clock@0 {
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compatible = "fixed-clock";
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reg = <0>;
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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clk_32k: clock@1 {
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compatible = "fixed-clock";
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reg = <1>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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&tegra_car {
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clocks = <&clk_32k> <&osc>;
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};
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};
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