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01f8162a85
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
318 lines
10 KiB
C
318 lines
10 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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/*
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* Please use this file (iwl-3945-hw.h) only for hardware-related definitions.
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* Please use iwl-3945-commands.h for uCode API definitions.
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* Please use iwl-3945.h for driver implementation definitions.
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*/
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#ifndef __iwl_3945_hw__
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#define __iwl_3945_hw__
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#include "iwl-eeprom.h"
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/*
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* uCode queue management definitions ...
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* Queue #4 is the command queue for 3945 and 4965.
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*/
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#define IWL_CMD_QUEUE_NUM 4
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/* Time constants */
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#define SHORT_SLOT_TIME 9
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#define LONG_SLOT_TIME 20
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/* RSSI to dBm */
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#define IWL39_RSSI_OFFSET 95
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/*
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* EEPROM related constants, enums, and structures.
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*/
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#define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7)
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/*
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* Mapping of a Tx power level, at factory calibration temperature,
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* to a radio/DSP gain table index.
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* One for each of 5 "sample" power levels in each band.
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* v_det is measured at the factory, using the 3945's built-in power amplifier
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* (PA) output voltage detector. This same detector is used during Tx of
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* long packets in normal operation to provide feedback as to proper output
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* level.
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* Data copied from EEPROM.
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* DO NOT ALTER THIS STRUCTURE!!!
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*/
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struct iwl3945_eeprom_txpower_sample {
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u8 gain_index; /* index into power (gain) setup table ... */
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s8 power; /* ... for this pwr level for this chnl group */
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u16 v_det; /* PA output voltage */
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} __attribute__ ((packed));
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/*
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* Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
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* One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
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* Tx power setup code interpolates between the 5 "sample" power levels
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* to determine the nominal setup for a requested power level.
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* Data copied from EEPROM.
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* DO NOT ALTER THIS STRUCTURE!!!
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*/
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struct iwl3945_eeprom_txpower_group {
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struct iwl3945_eeprom_txpower_sample samples[5]; /* 5 power levels */
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s32 a, b, c, d, e; /* coefficients for voltage->power
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* formula (signed) */
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s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
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* frequency (signed) */
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s8 saturation_power; /* highest power possible by h/w in this
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* band */
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u8 group_channel; /* "representative" channel # in this band */
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s16 temperature; /* h/w temperature at factory calib this band
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* (signed) */
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} __attribute__ ((packed));
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/*
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* Temperature-based Tx-power compensation data, not band-specific.
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* These coefficients are use to modify a/b/c/d/e coeffs based on
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* difference between current temperature and factory calib temperature.
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* Data copied from EEPROM.
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*/
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struct iwl3945_eeprom_temperature_corr {
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u32 Ta;
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u32 Tb;
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u32 Tc;
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u32 Td;
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u32 Te;
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} __attribute__ ((packed));
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/*
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* EEPROM map
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*/
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struct iwl3945_eeprom {
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u8 reserved0[16];
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u16 device_id; /* abs.ofs: 16 */
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u8 reserved1[2];
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u16 pmc; /* abs.ofs: 20 */
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u8 reserved2[20];
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u8 mac_address[6]; /* abs.ofs: 42 */
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u8 reserved3[58];
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u16 board_revision; /* abs.ofs: 106 */
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u8 reserved4[11];
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u8 board_pba_number[9]; /* abs.ofs: 119 */
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u8 reserved5[8];
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u16 version; /* abs.ofs: 136 */
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u8 sku_cap; /* abs.ofs: 138 */
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u8 leds_mode; /* abs.ofs: 139 */
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u16 oem_mode;
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u16 wowlan_mode; /* abs.ofs: 142 */
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u16 leds_time_interval; /* abs.ofs: 144 */
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u8 leds_off_time; /* abs.ofs: 146 */
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u8 leds_on_time; /* abs.ofs: 147 */
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u8 almgor_m_version; /* abs.ofs: 148 */
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u8 antenna_switch_type; /* abs.ofs: 149 */
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u8 reserved6[42];
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u8 sku_id[4]; /* abs.ofs: 192 */
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/*
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* Per-channel regulatory data.
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*
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* Each channel that *might* be supported by 3945 or 4965 has a fixed location
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* in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
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* txpower (MSB).
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*
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* Entries immediately below are for 20 MHz channel width. FAT (40 MHz)
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* channels (only for 4965, not supported by 3945) appear later in the EEPROM.
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*
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* 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
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*/
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u16 band_1_count; /* abs.ofs: 196 */
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struct iwl_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */
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/*
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* 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
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* 5.0 GHz channels 7, 8, 11, 12, 16
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* (4915-5080MHz) (none of these is ever supported)
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*/
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u16 band_2_count; /* abs.ofs: 226 */
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struct iwl_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */
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/*
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* 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
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* (5170-5320MHz)
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*/
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u16 band_3_count; /* abs.ofs: 254 */
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struct iwl_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */
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/*
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* 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
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* (5500-5700MHz)
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*/
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u16 band_4_count; /* abs.ofs: 280 */
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struct iwl_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */
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/*
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* 5.7 GHz channels 145, 149, 153, 157, 161, 165
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* (5725-5825MHz)
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*/
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u16 band_5_count; /* abs.ofs: 304 */
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struct iwl_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */
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u8 reserved9[194];
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/*
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* 3945 Txpower calibration data.
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*/
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#define IWL_NUM_TX_CALIB_GROUPS 5
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struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS];
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/* abs.ofs: 512 */
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struct iwl3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */
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u8 reserved16[172]; /* fill out to full 1024 byte block */
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} __attribute__ ((packed));
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#define IWL_EEPROM_IMAGE_SIZE 1024
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/* End of EEPROM */
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#define PCI_LINK_CTRL 0x0F0
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#define PCI_POWER_SOURCE 0x0C8
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#define PCI_REG_WUM8 0x0E8
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#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
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#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
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#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
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#define TFD_QUEUE_MIN 0
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#define TFD_QUEUE_MAX 6
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#define IWL_NUM_SCAN_RATES (2)
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#define IWL_DEFAULT_TX_RETRY 15
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/*********************************************/
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#define RFD_SIZE 4
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#define NUM_TFD_CHUNKS 4
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#define RX_QUEUE_SIZE 256
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#define RX_QUEUE_MASK 255
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#define RX_QUEUE_SIZE_LOG 8
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#define U32_PAD(n) ((4-(n))&0x3)
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#define TFD_CTL_COUNT_SET(n) (n << 24)
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#define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7)
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#define TFD_CTL_PAD_SET(n) (n << 28)
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#define TFD_CTL_PAD_GET(ctl) (ctl >> 28)
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/*
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* RX related structures and functions
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*/
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#define RX_FREE_BUFFERS 64
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#define RX_LOW_WATERMARK 8
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/* Sizes and addresses for instruction and data memory (SRAM) in
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* 3945's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
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#define IWL39_RTC_INST_LOWER_BOUND (0x000000)
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#define IWL39_RTC_INST_UPPER_BOUND (0x014000)
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#define IWL39_RTC_DATA_LOWER_BOUND (0x800000)
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#define IWL39_RTC_DATA_UPPER_BOUND (0x808000)
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#define IWL39_RTC_INST_SIZE (IWL39_RTC_INST_UPPER_BOUND - \
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IWL39_RTC_INST_LOWER_BOUND)
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#define IWL39_RTC_DATA_SIZE (IWL39_RTC_DATA_UPPER_BOUND - \
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IWL39_RTC_DATA_LOWER_BOUND)
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#define IWL39_MAX_INST_SIZE IWL39_RTC_INST_SIZE
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#define IWL39_MAX_DATA_SIZE IWL39_RTC_DATA_SIZE
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/* Size of uCode instruction memory in bootstrap state machine */
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#define IWL39_MAX_BSM_SIZE IWL39_RTC_INST_SIZE
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#define IWL39_MAX_NUM_QUEUES 8
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static inline int iwl3945_hw_valid_rtc_data_addr(u32 addr)
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{
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return (addr >= IWL39_RTC_DATA_LOWER_BOUND) &&
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(addr < IWL39_RTC_DATA_UPPER_BOUND);
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}
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/* Base physical address of iwl3945_shared is provided to FH_TSSR_CBB_BASE
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* and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */
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struct iwl3945_shared {
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__le32 tx_base_ptr[8];
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} __attribute__ ((packed));
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static inline u8 iwl3945_hw_get_rate(__le16 rate_n_flags)
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{
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return le16_to_cpu(rate_n_flags) & 0xFF;
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}
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static inline u16 iwl3945_hw_get_rate_n_flags(__le16 rate_n_flags)
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{
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return le16_to_cpu(rate_n_flags);
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}
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static inline __le16 iwl3945_hw_set_rate_n_flags(u8 rate, u16 flags)
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{
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return cpu_to_le16((u16)rate|flags);
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}
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#endif
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