mirror of
https://github.com/torvalds/linux.git
synced 2024-12-28 13:51:44 +00:00
7bc082d7e9
Cleanup DBI read and write APIs by removing leading "__" (underscore)
from their names as there is no reason to have leading underscores
in the first place in the function definition.
Remove dbi/dbi2 base address parameters as the same behaviour can be
obtained through read and write APIs. Since dw_pcie_{readl/writel}_dbi()
APIs can't be used for ATU read/write as ATU base address could be
different from DBI base address, implement ATU read/write APIs using ATU
base address without using dw_pcie_{readl/writel}_dbi() APIs.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
466 lines
11 KiB
C
466 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Synopsys DesignWare PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*/
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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int dw_pcie_read(void __iomem *addr, int size, u32 *val)
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{
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if (!IS_ALIGNED((uintptr_t)addr, size)) {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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if (size == 4) {
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*val = readl(addr);
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} else if (size == 2) {
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*val = readw(addr);
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} else if (size == 1) {
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*val = readb(addr);
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} else {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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int dw_pcie_write(void __iomem *addr, int size, u32 val)
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{
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if (!IS_ALIGNED((uintptr_t)addr, size))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (size == 4)
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writel(val, addr);
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else if (size == 2)
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writew(val, addr);
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else if (size == 1)
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writeb(val, addr);
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
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{
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int ret;
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u32 val;
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if (pci->ops->read_dbi)
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return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
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ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
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if (ret)
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dev_err(pci->dev, "Read DBI address failed\n");
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return val;
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}
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void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
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{
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int ret;
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if (pci->ops->write_dbi) {
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pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
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return;
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}
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ret = dw_pcie_write(pci->dbi_base + reg, size, val);
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if (ret)
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dev_err(pci->dev, "Write DBI address failed\n");
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}
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u32 dw_pcie_read_dbi2(struct dw_pcie *pci, u32 reg, size_t size)
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{
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int ret;
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u32 val;
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if (pci->ops->read_dbi2)
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return pci->ops->read_dbi2(pci, pci->dbi_base2, reg, size);
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ret = dw_pcie_read(pci->dbi_base2 + reg, size, &val);
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if (ret)
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dev_err(pci->dev, "read DBI address failed\n");
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return val;
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}
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void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
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{
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int ret;
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if (pci->ops->write_dbi2) {
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pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
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return;
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}
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ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
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if (ret)
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dev_err(pci->dev, "write DBI address failed\n");
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}
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u32 dw_pcie_read_atu(struct dw_pcie *pci, u32 reg, size_t size)
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{
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int ret;
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u32 val;
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if (pci->ops->read_dbi)
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return pci->ops->read_dbi(pci, pci->atu_base, reg, size);
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ret = dw_pcie_read(pci->atu_base + reg, size, &val);
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if (ret)
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dev_err(pci->dev, "Read ATU address failed\n");
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return val;
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}
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void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
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{
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int ret;
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if (pci->ops->write_dbi) {
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pci->ops->write_dbi(pci, pci->atu_base, reg, size, val);
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return;
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}
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ret = dw_pcie_write(pci->atu_base + reg, size, val);
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if (ret)
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dev_err(pci->dev, "Write ATU address failed\n");
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}
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static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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return dw_pcie_readl_atu(pci, offset + reg);
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}
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static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
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u32 val)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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dw_pcie_writel_atu(pci, offset + reg, val);
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}
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static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
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int type, u64 cpu_addr,
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u64 pci_addr, u32 size)
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{
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u32 retries, val;
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
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lower_32_bits(cpu_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
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upper_32_bits(cpu_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
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lower_32_bits(cpu_addr + size - 1));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
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lower_32_bits(pci_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
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upper_32_bits(pci_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
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type);
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
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PCIE_ATU_ENABLE);
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_ob_unroll(pci, index,
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PCIE_ATU_UNR_REGION_CTRL2);
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if (val & PCIE_ATU_ENABLE)
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return;
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mdelay(LINK_WAIT_IATU);
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}
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dev_err(pci->dev, "Outbound iATU is not being enabled\n");
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}
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void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
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u64 cpu_addr, u64 pci_addr, u32 size)
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{
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u32 retries, val;
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if (pci->ops->cpu_addr_fixup)
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cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
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if (pci->iatu_unroll_enabled) {
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dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
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pci_addr, size);
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return;
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}
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dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
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PCIE_ATU_REGION_OUTBOUND | index);
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dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
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lower_32_bits(cpu_addr));
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dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
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upper_32_bits(cpu_addr));
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dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
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lower_32_bits(cpu_addr + size - 1));
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dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
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lower_32_bits(pci_addr));
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dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
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upper_32_bits(pci_addr));
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dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
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dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
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if (val & PCIE_ATU_ENABLE)
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return;
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mdelay(LINK_WAIT_IATU);
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}
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dev_err(pci->dev, "Outbound iATU is not being enabled\n");
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}
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static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
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{
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u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
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return dw_pcie_readl_atu(pci, offset + reg);
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}
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static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
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u32 val)
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{
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u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
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dw_pcie_writel_atu(pci, offset + reg, val);
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}
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static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
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int bar, u64 cpu_addr,
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enum dw_pcie_as_type as_type)
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{
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int type;
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u32 retries, val;
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
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lower_32_bits(cpu_addr));
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
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upper_32_bits(cpu_addr));
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switch (as_type) {
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case DW_PCIE_AS_MEM:
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type = PCIE_ATU_TYPE_MEM;
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break;
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case DW_PCIE_AS_IO:
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type = PCIE_ATU_TYPE_IO;
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break;
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default:
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return -EINVAL;
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}
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
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PCIE_ATU_ENABLE |
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PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_ib_unroll(pci, index,
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PCIE_ATU_UNR_REGION_CTRL2);
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if (val & PCIE_ATU_ENABLE)
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return 0;
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mdelay(LINK_WAIT_IATU);
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}
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dev_err(pci->dev, "Inbound iATU is not being enabled\n");
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return -EBUSY;
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}
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int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
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u64 cpu_addr, enum dw_pcie_as_type as_type)
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{
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int type;
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u32 retries, val;
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if (pci->iatu_unroll_enabled)
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return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
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cpu_addr, as_type);
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dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
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index);
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dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
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dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
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switch (as_type) {
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case DW_PCIE_AS_MEM:
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type = PCIE_ATU_TYPE_MEM;
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break;
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case DW_PCIE_AS_IO:
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type = PCIE_ATU_TYPE_IO;
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break;
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default:
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return -EINVAL;
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}
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dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
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dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
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| PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
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if (val & PCIE_ATU_ENABLE)
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return 0;
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mdelay(LINK_WAIT_IATU);
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}
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dev_err(pci->dev, "Inbound iATU is not being enabled\n");
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return -EBUSY;
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}
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void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
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enum dw_pcie_region_type type)
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{
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int region;
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switch (type) {
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case DW_PCIE_REGION_INBOUND:
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region = PCIE_ATU_REGION_INBOUND;
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break;
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case DW_PCIE_REGION_OUTBOUND:
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region = PCIE_ATU_REGION_OUTBOUND;
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break;
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default:
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return;
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}
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dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
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dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, (u32)~PCIE_ATU_ENABLE);
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}
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int dw_pcie_wait_for_link(struct dw_pcie *pci)
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{
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int retries;
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/* Check if the link is up or not */
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for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
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if (dw_pcie_link_up(pci)) {
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dev_info(pci->dev, "Link up\n");
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return 0;
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}
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usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
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}
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dev_err(pci->dev, "Phy link never came up\n");
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return -ETIMEDOUT;
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}
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int dw_pcie_link_up(struct dw_pcie *pci)
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{
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u32 val;
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if (pci->ops->link_up)
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return pci->ops->link_up(pci);
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val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
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return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
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(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
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}
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static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
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{
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u32 val;
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val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
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if (val == 0xffffffff)
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return 1;
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return 0;
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}
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void dw_pcie_setup(struct dw_pcie *pci)
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{
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int ret;
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u32 val;
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u32 lanes;
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struct device *dev = pci->dev;
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struct device_node *np = dev->of_node;
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if (pci->version >= 0x480A || (!pci->version &&
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dw_pcie_iatu_unroll_enabled(pci))) {
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pci->iatu_unroll_enabled = true;
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if (!pci->atu_base)
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pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
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}
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dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
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"enabled" : "disabled");
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ret = of_property_read_u32(np, "num-lanes", &lanes);
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if (ret)
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lanes = 0;
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/* Set the number of lanes */
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val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
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val &= ~PORT_LINK_MODE_MASK;
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switch (lanes) {
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case 1:
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val |= PORT_LINK_MODE_1_LANES;
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break;
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case 2:
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val |= PORT_LINK_MODE_2_LANES;
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break;
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case 4:
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val |= PORT_LINK_MODE_4_LANES;
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break;
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case 8:
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val |= PORT_LINK_MODE_8_LANES;
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break;
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default:
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dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
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return;
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}
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dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
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/* Set link width speed control register */
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val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
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val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
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switch (lanes) {
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case 1:
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val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
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break;
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case 2:
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val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
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break;
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case 4:
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val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
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break;
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case 8:
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val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
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break;
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}
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dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
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}
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