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7bb83f6d08
Switch 2 has an 88e1545 PHY behind it, which is a quad PHY. Only the
first three PHYs are used, the remaining PHY is unused. When we wire
up the SFF sockets in a later commit, the omission of this causes the
fourth PHY to be used for port 3. Specifying the PHYs in DT avoids
the auto-probing of the bus, and discovery of this PHY.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
497 lines
10 KiB
Plaintext
497 lines
10 KiB
Plaintext
/*
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* Copyright (C) 2015, 2016 Zodiac Inflight Innovations
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*
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* Based on an original 'vf610-twr.dts' which is Copyright 2015,
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* Freescale Semiconductor, Inc.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "vf610-zii-dev.dtsi"
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/ {
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model = "ZII VF610 Development Board, Rev B";
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compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
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mdio-mux {
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compatible = "mdio-mux-gpio";
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pinctrl-0 = <&pinctrl_mdio_mux>;
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pinctrl-names = "default";
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gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
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&gpio0 9 GPIO_ACTIVE_HIGH
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&gpio0 24 GPIO_ACTIVE_HIGH
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&gpio0 25 GPIO_ACTIVE_HIGH>;
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mdio-parent-bus = <&mdio1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio_mux_1: mdio@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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switch0: switch@0 {
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compatible = "marvell,mv88e6085";
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pinctrl-0 = <&pinctrl_gpio_switch0>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dsa,member = <0 0>;
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interrupt-parent = <&gpio0>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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eeprom-length = <512>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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phy-handle = <&switch0phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&switch0phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&switch0phy2>;
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};
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switch0port5: port@5 {
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reg = <5>;
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label = "dsa";
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phy-mode = "rgmii-txid";
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link = <&switch1port6
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&switch2port9>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&fec1>;
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy0: switch0phy0@0 {
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reg = <0>;
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interrupt-parent = <&switch0>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
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};
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switch0phy1: switch1phy0@1 {
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reg = <1>;
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interrupt-parent = <&switch0>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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};
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switch0phy2: switch1phy0@2 {
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reg = <2>;
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interrupt-parent = <&switch0>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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};
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mdio_mux_2: mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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switch1: switch@0 {
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compatible = "marvell,mv88e6085";
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pinctrl-0 = <&pinctrl_gpio_switch1>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dsa,member = <0 1>;
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interrupt-parent = <&gpio0>;
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interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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eeprom-length = <512>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan3";
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phy-handle = <&switch1phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-handle = <&switch1phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan5";
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phy-handle = <&switch1phy2>;
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};
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switch1port5: port@5 {
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reg = <5>;
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label = "dsa";
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link = <&switch2port9>;
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phy-mode = "rgmii-txid";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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switch1port6: port@6 {
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reg = <6>;
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label = "dsa";
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phy-mode = "rgmii-txid";
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link = <&switch0port5>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch1phy0: switch1phy0@0 {
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reg = <0>;
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interrupt-parent = <&switch1>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
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};
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switch1phy1: switch1phy0@1 {
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reg = <1>;
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interrupt-parent = <&switch1>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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};
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switch1phy2: switch1phy0@2 {
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reg = <2>;
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interrupt-parent = <&switch1>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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};
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mdio_mux_4: mdio@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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switch2: switch@0 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dsa,member = <0 2>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan6";
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phy-handle = <&switch2phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan7";
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phy-handle = <&switch2phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan8";
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phy-handle = <&switch2phy2>;
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};
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port@3 {
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reg = <3>;
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label = "optical3";
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fixed-link {
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speed = <1000>;
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full-duplex;
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link-gpios = <&gpio6 2
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GPIO_ACTIVE_HIGH>;
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};
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};
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port@4 {
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reg = <4>;
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label = "optical4";
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fixed-link {
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speed = <1000>;
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full-duplex;
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link-gpios = <&gpio6 3
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GPIO_ACTIVE_HIGH>;
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};
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};
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switch2port9: port@9 {
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reg = <9>;
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label = "dsa";
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phy-mode = "rgmii-txid";
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link = <&switch1port5
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&switch0port5>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch2phy0: phy@0 {
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reg = <0>;
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};
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switch2phy1: phy@1 {
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reg = <1>;
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};
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switch2phy2: phy@2 {
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reg = <2>;
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};
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};
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};
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};
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mdio_mux_8: mdio@8 {
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reg = <8>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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spi0 {
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compatible = "spi-gpio";
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pinctrl-0 = <&pinctrl_gpio_spi0>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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cs-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
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&gpio1 8 GPIO_ACTIVE_HIGH>;
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num-chipselects = <2>;
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m25p128@0 {
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compatible = "m25p128", "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <1000000>;
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};
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at93c46d@1 {
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compatible = "atmel,at93c46d";
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pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
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pinctrl-names = "default";
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#address-cells = <0>;
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#size-cells = <0>;
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reg = <1>;
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spi-max-frequency = <500000>;
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spi-cs-high;
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data-size = <16>;
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select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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status = "okay";
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gpio5: pca9554@20 {
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compatible = "nxp,pca9554";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio6: pca9554@22 {
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compatible = "nxp,pca9554";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pca9554_22>;
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gpio3>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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tca9548@70 {
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compatible = "nxp,pca9548";
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pinctrl-0 = <&pinctrl_i2c_mux_reset>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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sfp1: at24c04@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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sfp2: at24c04@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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sfp3: at24c04@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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sfp4: at24c04@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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};
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};
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};
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&iomuxc {
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pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
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fsl,pins = <
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VF610_PAD_PTE27__GPIO_132 0x33e2
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>;
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};
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pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
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fsl,pins = <
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VF610_PAD_PTB22__GPIO_44 0x33e2
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VF610_PAD_PTB21__GPIO_43 0x33e2
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VF610_PAD_PTB20__GPIO_42 0x33e1
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VF610_PAD_PTB19__GPIO_41 0x33e2
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VF610_PAD_PTB18__GPIO_40 0x33e2
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>;
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};
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pinctrl_mdio_mux: pinctrl-mdio-mux {
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fsl,pins = <
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VF610_PAD_PTA18__GPIO_8 0x31c2
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VF610_PAD_PTA19__GPIO_9 0x31c2
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VF610_PAD_PTB2__GPIO_24 0x31c2
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VF610_PAD_PTB3__GPIO_25 0x31c2
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>;
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};
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pinctrl_pca9554_22: pinctrl-pca95540-22 {
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fsl,pins = <
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VF610_PAD_PTB28__GPIO_98 0x219d
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>;
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};
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};
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