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7a2207a0e1
no-one use it and it's nearly impossible get a board to work on it and the Mainline implementation was never finished Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com> Cc: Andrew Victor <linux@maxim.org.za>
196 lines
6.0 KiB
C
196 lines
6.0 KiB
C
/*
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* arch/arm/mach-at91/include/mach/cpu.h
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*
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* Copyright (C) 2006 SAN People
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __ASM_ARCH_CPU_H
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#define __ASM_ARCH_CPU_H
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#include <mach/hardware.h>
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#include <mach/at91_dbgu.h>
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#define ARCH_ID_AT91RM9200 0x09290780
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#define ARCH_ID_AT91SAM9260 0x019803a0
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#define ARCH_ID_AT91SAM9261 0x019703a0
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#define ARCH_ID_AT91SAM9263 0x019607a0
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#define ARCH_ID_AT91SAM9G10 0x019903a0
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#define ARCH_ID_AT91SAM9G20 0x019905a0
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#define ARCH_ID_AT91SAM9RL64 0x019b03a0
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#define ARCH_ID_AT91SAM9G45 0x819b05a0
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#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
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#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
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#define ARCH_ID_AT91SAM9X5 0x819a05a0
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#define ARCH_ID_AT91CAP9 0x039A03A0
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#define ARCH_ID_AT91SAM9XE128 0x329973a0
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#define ARCH_ID_AT91SAM9XE256 0x329a93a0
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#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
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#define ARCH_ID_AT91M40800 0x14080044
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#define ARCH_ID_AT91R40807 0x44080746
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#define ARCH_ID_AT91M40807 0x14080745
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#define ARCH_ID_AT91R40008 0x44000840
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static inline unsigned long at91_cpu_identify(void)
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{
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return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
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}
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static inline unsigned long at91_cpu_fully_identify(void)
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{
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return at91_sys_read(AT91_DBGU_CIDR);
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}
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#define ARCH_EXID_AT91SAM9M11 0x00000001
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#define ARCH_EXID_AT91SAM9M10 0x00000002
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#define ARCH_EXID_AT91SAM9G46 0x00000003
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#define ARCH_EXID_AT91SAM9G45 0x00000004
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#define ARCH_EXID_AT91SAM9G15 0x00000000
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#define ARCH_EXID_AT91SAM9G35 0x00000001
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#define ARCH_EXID_AT91SAM9X35 0x00000002
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#define ARCH_EXID_AT91SAM9G25 0x00000003
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#define ARCH_EXID_AT91SAM9X25 0x00000004
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static inline unsigned long at91_exid_identify(void)
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{
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return at91_sys_read(AT91_DBGU_EXID);
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}
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#define ARCH_FAMILY_AT91X92 0x09200000
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#define ARCH_FAMILY_AT91SAM9 0x01900000
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#define ARCH_FAMILY_AT91SAM9XE 0x02900000
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static inline unsigned long at91_arch_identify(void)
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{
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return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH);
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}
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#ifdef CONFIG_ARCH_AT91CAP9
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#include <mach/at91_pmc.h>
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#define ARCH_REVISION_CAP9_B 0x399
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#define ARCH_REVISION_CAP9_C 0x601
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static inline unsigned long at91cap9_rev_identify(void)
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{
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return (at91_sys_read(AT91_PMC_VER));
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}
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#endif
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#ifdef CONFIG_ARCH_AT91RM9200
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extern int rm9200_type;
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#define ARCH_REVISON_9200_BGA (0 << 0)
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#define ARCH_REVISON_9200_PQFP (1 << 0)
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#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
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#define cpu_is_at91rm9200_bga() (!cpu_is_at91rm9200_pqfp())
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#define cpu_is_at91rm9200_pqfp() (cpu_is_at91rm9200() && rm9200_type & ARCH_REVISON_9200_PQFP)
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#else
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#define cpu_is_at91rm9200() (0)
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#define cpu_is_at91rm9200_bga() (0)
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#define cpu_is_at91rm9200_pqfp() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9260
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#define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE)
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#define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe())
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#else
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#define cpu_is_at91sam9xe() (0)
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#define cpu_is_at91sam9260() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9G20
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#define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
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#else
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#define cpu_is_at91sam9g20() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9261
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#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
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#else
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#define cpu_is_at91sam9261() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9G10
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#define cpu_is_at91sam9g10() ((at91_cpu_identify() & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10)
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#else
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#define cpu_is_at91sam9g10() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9263
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#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
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#else
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#define cpu_is_at91sam9263() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9RL
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#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
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#else
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#define cpu_is_at91sam9rl() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9G45
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#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
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#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
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#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \
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(at91_exid_identify() == ARCH_EXID_AT91SAM9M10))
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#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \
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(at91_exid_identify() == ARCH_EXID_AT91SAM9G46))
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#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \
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(at91_exid_identify() == ARCH_EXID_AT91SAM9M11))
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#else
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#define cpu_is_at91sam9g45() (0)
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#define cpu_is_at91sam9g45es() (0)
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#define cpu_is_at91sam9m10() (0)
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#define cpu_is_at91sam9g46() (0)
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#define cpu_is_at91sam9m11() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9X5
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#define cpu_is_at91sam9x5() (at91_cpu_identify() == ARCH_ID_AT91SAM9X5)
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#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
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(at91_exid_identify() == ARCH_EXID_AT91SAM9G15))
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#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
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(at91_exid_identify() == ARCH_EXID_AT91SAM9G35))
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#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
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(at91_exid_identify() == ARCH_EXID_AT91SAM9X35))
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#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
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(at91_exid_identify() == ARCH_EXID_AT91SAM9G25))
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#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
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(at91_exid_identify() == ARCH_EXID_AT91SAM9X25))
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#else
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#define cpu_is_at91sam9x5() (0)
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#define cpu_is_at91sam9g15() (0)
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#define cpu_is_at91sam9g35() (0)
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#define cpu_is_at91sam9x35() (0)
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#define cpu_is_at91sam9g25() (0)
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#define cpu_is_at91sam9x25() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91CAP9
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#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
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#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
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#define cpu_is_at91cap9_revC() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_C)
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#else
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#define cpu_is_at91cap9() (0)
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#define cpu_is_at91cap9_revB() (0)
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#define cpu_is_at91cap9_revC() (0)
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#endif
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/*
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* Since this is ARM, we will never run on any AVR32 CPU. But these
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* definitions may reduce clutter in common drivers.
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*/
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#define cpu_is_at32ap7000() (0)
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#endif
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