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593cd87112
The FSMC actually has a standard ARM PrimeCell ID register, and the "revision" part of that register contains the thing that the code is looking at. Reuse the infrastructure from the AMBA bus abstraction and rid local defines. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
914 lines
23 KiB
C
914 lines
23 KiB
C
/*
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* drivers/mtd/nand/fsmc_nand.c
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*
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* ST Microelectronics
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* Flexible Static Memory Controller (FSMC)
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* Driver for NAND portions
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*
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* Copyright © 2010 ST Microelectronics
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* Vipin Kumar <vipin.kumar@st.com>
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* Ashish Priyadarshi
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*
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* Based on drivers/mtd/nand/nomadik_nand.c
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/resource.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/partitions.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/mtd/fsmc.h>
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#include <linux/amba/bus.h>
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#include <mtd/mtd-abi.h>
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static struct nand_ecclayout fsmc_ecc1_layout = {
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.eccbytes = 24,
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.eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
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66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
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.oobfree = {
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{.offset = 8, .length = 8},
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{.offset = 24, .length = 8},
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{.offset = 40, .length = 8},
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{.offset = 56, .length = 8},
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{.offset = 72, .length = 8},
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{.offset = 88, .length = 8},
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{.offset = 104, .length = 8},
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{.offset = 120, .length = 8}
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}
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};
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static struct nand_ecclayout fsmc_ecc4_lp_layout = {
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.eccbytes = 104,
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.eccpos = { 2, 3, 4, 5, 6, 7, 8,
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9, 10, 11, 12, 13, 14,
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18, 19, 20, 21, 22, 23, 24,
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25, 26, 27, 28, 29, 30,
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34, 35, 36, 37, 38, 39, 40,
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41, 42, 43, 44, 45, 46,
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50, 51, 52, 53, 54, 55, 56,
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57, 58, 59, 60, 61, 62,
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66, 67, 68, 69, 70, 71, 72,
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73, 74, 75, 76, 77, 78,
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82, 83, 84, 85, 86, 87, 88,
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89, 90, 91, 92, 93, 94,
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98, 99, 100, 101, 102, 103, 104,
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105, 106, 107, 108, 109, 110,
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114, 115, 116, 117, 118, 119, 120,
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121, 122, 123, 124, 125, 126
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},
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.oobfree = {
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{.offset = 15, .length = 3},
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{.offset = 31, .length = 3},
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{.offset = 47, .length = 3},
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{.offset = 63, .length = 3},
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{.offset = 79, .length = 3},
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{.offset = 95, .length = 3},
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{.offset = 111, .length = 3},
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{.offset = 127, .length = 1}
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}
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};
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/*
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* ECC placement definitions in oobfree type format.
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* There are 13 bytes of ecc for every 512 byte block and it has to be read
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* consecutively and immediately after the 512 byte data block for hardware to
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* generate the error bit offsets in 512 byte data.
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* Managing the ecc bytes in the following way makes it easier for software to
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* read ecc bytes consecutive to data bytes. This way is similar to
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* oobfree structure maintained already in generic nand driver
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*/
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static struct fsmc_eccplace fsmc_ecc4_lp_place = {
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.eccplace = {
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{.offset = 2, .length = 13},
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{.offset = 18, .length = 13},
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{.offset = 34, .length = 13},
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{.offset = 50, .length = 13},
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{.offset = 66, .length = 13},
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{.offset = 82, .length = 13},
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{.offset = 98, .length = 13},
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{.offset = 114, .length = 13}
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}
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};
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static struct nand_ecclayout fsmc_ecc4_sp_layout = {
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.eccbytes = 13,
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.eccpos = { 0, 1, 2, 3, 6, 7, 8,
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9, 10, 11, 12, 13, 14
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},
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.oobfree = {
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{.offset = 15, .length = 1},
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}
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};
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static struct fsmc_eccplace fsmc_ecc4_sp_place = {
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.eccplace = {
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{.offset = 0, .length = 4},
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{.offset = 6, .length = 9}
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}
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};
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#ifdef CONFIG_MTD_PARTITIONS
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/*
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* Default partition tables to be used if the partition information not
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* provided through platform data.
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*
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* Default partition layout for small page(= 512 bytes) devices
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* Size for "Root file system" is updated in driver based on actual device size
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*/
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static struct mtd_partition partition_info_16KB_blk[] = {
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{
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.name = "X-loader",
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.offset = 0,
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.size = 4*0x4000,
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},
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{
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.name = "U-Boot",
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.offset = 0x10000,
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.size = 20*0x4000,
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},
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{
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.name = "Kernel",
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.offset = 0x60000,
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.size = 256*0x4000,
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},
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{
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.name = "Root File System",
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.offset = 0x460000,
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.size = 0,
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},
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};
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/*
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* Default partition layout for large page(> 512 bytes) devices
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* Size for "Root file system" is updated in driver based on actual device size
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*/
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static struct mtd_partition partition_info_128KB_blk[] = {
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{
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.name = "X-loader",
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.offset = 0,
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.size = 4*0x20000,
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},
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{
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.name = "U-Boot",
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.offset = 0x80000,
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.size = 12*0x20000,
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},
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{
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.name = "Kernel",
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.offset = 0x200000,
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.size = 48*0x20000,
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},
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{
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.name = "Root File System",
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.offset = 0x800000,
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.size = 0,
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},
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};
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#ifdef CONFIG_MTD_CMDLINE_PARTS
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const char *part_probes[] = { "cmdlinepart", NULL };
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#endif
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#endif
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/**
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* struct fsmc_nand_data - structure for FSMC NAND device state
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*
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* @pid: Part ID on the AMBA PrimeCell format
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* @mtd: MTD info for a NAND flash.
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* @nand: Chip related info for a NAND flash.
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* @partitions: Partition info for a NAND Flash.
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* @nr_partitions: Total number of partition of a NAND flash.
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*
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* @ecc_place: ECC placing locations in oobfree type format.
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* @bank: Bank number for probed device.
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* @clk: Clock structure for FSMC.
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*
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* @data_va: NAND port for Data.
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* @cmd_va: NAND port for Command.
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* @addr_va: NAND port for Address.
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* @regs_va: FSMC regs base address.
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*/
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struct fsmc_nand_data {
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u32 pid;
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struct mtd_info mtd;
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struct nand_chip nand;
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struct mtd_partition *partitions;
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unsigned int nr_partitions;
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struct fsmc_eccplace *ecc_place;
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unsigned int bank;
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struct clk *clk;
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struct resource *resregs;
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struct resource *rescmd;
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struct resource *resaddr;
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struct resource *resdata;
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void __iomem *data_va;
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void __iomem *cmd_va;
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void __iomem *addr_va;
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void __iomem *regs_va;
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void (*select_chip)(uint32_t bank, uint32_t busw);
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};
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/* Assert CS signal based on chipnr */
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static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsmc_nand_data *host;
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host = container_of(mtd, struct fsmc_nand_data, mtd);
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switch (chipnr) {
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case -1:
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chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
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break;
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case 0:
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case 1:
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case 2:
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case 3:
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if (host->select_chip)
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host->select_chip(chipnr,
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chip->options & NAND_BUSWIDTH_16);
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break;
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default:
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BUG();
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}
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}
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/*
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* fsmc_cmd_ctrl - For facilitaing Hardware access
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* This routine allows hardware specific access to control-lines(ALE,CLE)
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*/
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static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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struct fsmc_nand_data *host = container_of(mtd,
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struct fsmc_nand_data, mtd);
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struct fsmc_regs *regs = host->regs_va;
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unsigned int bank = host->bank;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_CLE) {
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this->IO_ADDR_R = (void __iomem *)host->cmd_va;
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this->IO_ADDR_W = (void __iomem *)host->cmd_va;
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} else if (ctrl & NAND_ALE) {
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this->IO_ADDR_R = (void __iomem *)host->addr_va;
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this->IO_ADDR_W = (void __iomem *)host->addr_va;
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} else {
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this->IO_ADDR_R = (void __iomem *)host->data_va;
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this->IO_ADDR_W = (void __iomem *)host->data_va;
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}
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if (ctrl & NAND_NCE) {
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writel(readl(®s->bank_regs[bank].pc) | FSMC_ENABLE,
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®s->bank_regs[bank].pc);
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} else {
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writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ENABLE,
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®s->bank_regs[bank].pc);
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}
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}
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mb();
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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/*
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* fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
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*
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* This routine initializes timing parameters related to NAND memory access in
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* FSMC registers
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*/
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static void __init fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
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uint32_t busw)
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{
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uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
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if (busw)
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writel(value | FSMC_DEVWID_16, ®s->bank_regs[bank].pc);
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else
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writel(value | FSMC_DEVWID_8, ®s->bank_regs[bank].pc);
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writel(readl(®s->bank_regs[bank].pc) | FSMC_TCLR_1 | FSMC_TAR_1,
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®s->bank_regs[bank].pc);
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writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
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®s->bank_regs[bank].comm);
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writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
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®s->bank_regs[bank].attrib);
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}
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/*
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* fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
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*/
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static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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struct fsmc_nand_data *host = container_of(mtd,
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struct fsmc_nand_data, mtd);
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struct fsmc_regs *regs = host->regs_va;
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uint32_t bank = host->bank;
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writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256,
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®s->bank_regs[bank].pc);
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writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCEN,
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®s->bank_regs[bank].pc);
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writel(readl(®s->bank_regs[bank].pc) | FSMC_ECCEN,
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®s->bank_regs[bank].pc);
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}
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/*
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* fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
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* FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction upto
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* max of 8-bits)
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*/
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static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
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uint8_t *ecc)
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{
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struct fsmc_nand_data *host = container_of(mtd,
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struct fsmc_nand_data, mtd);
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struct fsmc_regs *regs = host->regs_va;
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uint32_t bank = host->bank;
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uint32_t ecc_tmp;
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unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
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do {
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if (readl(®s->bank_regs[bank].sts) & FSMC_CODE_RDY)
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break;
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else
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cond_resched();
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} while (!time_after_eq(jiffies, deadline));
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ecc_tmp = readl(®s->bank_regs[bank].ecc1);
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ecc[0] = (uint8_t) (ecc_tmp >> 0);
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ecc[1] = (uint8_t) (ecc_tmp >> 8);
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ecc[2] = (uint8_t) (ecc_tmp >> 16);
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ecc[3] = (uint8_t) (ecc_tmp >> 24);
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ecc_tmp = readl(®s->bank_regs[bank].ecc2);
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ecc[4] = (uint8_t) (ecc_tmp >> 0);
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ecc[5] = (uint8_t) (ecc_tmp >> 8);
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ecc[6] = (uint8_t) (ecc_tmp >> 16);
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ecc[7] = (uint8_t) (ecc_tmp >> 24);
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ecc_tmp = readl(®s->bank_regs[bank].ecc3);
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ecc[8] = (uint8_t) (ecc_tmp >> 0);
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ecc[9] = (uint8_t) (ecc_tmp >> 8);
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ecc[10] = (uint8_t) (ecc_tmp >> 16);
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ecc[11] = (uint8_t) (ecc_tmp >> 24);
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ecc_tmp = readl(®s->bank_regs[bank].sts);
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ecc[12] = (uint8_t) (ecc_tmp >> 16);
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return 0;
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}
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/*
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* fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
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* FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction upto
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* max of 1-bit)
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*/
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static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
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uint8_t *ecc)
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{
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struct fsmc_nand_data *host = container_of(mtd,
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struct fsmc_nand_data, mtd);
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struct fsmc_regs *regs = host->regs_va;
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uint32_t bank = host->bank;
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uint32_t ecc_tmp;
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ecc_tmp = readl(®s->bank_regs[bank].ecc1);
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ecc[0] = (uint8_t) (ecc_tmp >> 0);
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ecc[1] = (uint8_t) (ecc_tmp >> 8);
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ecc[2] = (uint8_t) (ecc_tmp >> 16);
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return 0;
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}
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/*
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* fsmc_read_page_hwecc
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* @mtd: mtd info structure
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* @chip: nand chip info structure
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* @buf: buffer to store read data
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* @page: page number to read
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*
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* This routine is needed for fsmc verison 8 as reading from NAND chip has to be
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* performed in a strict sequence as follows:
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* data(512 byte) -> ecc(13 byte)
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* After this read, fsmc hardware generates and reports error data bits(upto a
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* max of 8 bits)
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*/
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static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int page)
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{
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struct fsmc_nand_data *host = container_of(mtd,
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struct fsmc_nand_data, mtd);
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struct fsmc_eccplace *ecc_place = host->ecc_place;
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int i, j, s, stat, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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uint8_t *p = buf;
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uint8_t *ecc_calc = chip->buffers->ecccalc;
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uint8_t *ecc_code = chip->buffers->ecccode;
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int off, len, group = 0;
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/*
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* ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
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* end up reading 14 bytes (7 words) from oob. The local array is
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* to maintain word alignment
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*/
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uint16_t ecc_oob[7];
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uint8_t *oob = (uint8_t *)&ecc_oob[0];
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for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
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chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
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chip->ecc.hwctl(mtd, NAND_ECC_READ);
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chip->read_buf(mtd, p, eccsize);
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for (j = 0; j < eccbytes;) {
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off = ecc_place->eccplace[group].offset;
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len = ecc_place->eccplace[group].length;
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group++;
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/*
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* length is intentionally kept a higher multiple of 2
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* to read at least 13 bytes even in case of 16 bit NAND
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* devices
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*/
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len = roundup(len, 2);
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chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
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chip->read_buf(mtd, oob + j, len);
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j += len;
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}
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memcpy(&ecc_code[i], oob, 13);
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chip->ecc.calculate(mtd, p, &ecc_calc[i]);
|
|
|
|
stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
|
|
if (stat < 0)
|
|
mtd->ecc_stats.failed++;
|
|
else
|
|
mtd->ecc_stats.corrected += stat;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* fsmc_correct_data
|
|
* @mtd: mtd info structure
|
|
* @dat: buffer of read data
|
|
* @read_ecc: ecc read from device spare area
|
|
* @calc_ecc: ecc calculated from read data
|
|
*
|
|
* calc_ecc is a 104 bit information containing maximum of 8 error
|
|
* offset informations of 13 bits each in 512 bytes of read data.
|
|
*/
|
|
static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
|
|
uint8_t *read_ecc, uint8_t *calc_ecc)
|
|
{
|
|
struct fsmc_nand_data *host = container_of(mtd,
|
|
struct fsmc_nand_data, mtd);
|
|
struct fsmc_regs *regs = host->regs_va;
|
|
unsigned int bank = host->bank;
|
|
uint16_t err_idx[8];
|
|
uint64_t ecc_data[2];
|
|
uint32_t num_err, i;
|
|
|
|
/* The calculated ecc is actually the correction index in data */
|
|
memcpy(ecc_data, calc_ecc, 13);
|
|
|
|
/*
|
|
* ------------------- calc_ecc[] bit wise -----------|--13 bits--|
|
|
* |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
|
|
*
|
|
* calc_ecc is a 104 bit information containing maximum of 8 error
|
|
* offset informations of 13 bits each. calc_ecc is copied into a
|
|
* uint64_t array and error offset indexes are populated in err_idx
|
|
* array
|
|
*/
|
|
for (i = 0; i < 8; i++) {
|
|
if (i == 4) {
|
|
err_idx[4] = ((ecc_data[1] & 0x1) << 12) | ecc_data[0];
|
|
ecc_data[1] >>= 1;
|
|
continue;
|
|
}
|
|
err_idx[i] = (ecc_data[i/4] & 0x1FFF);
|
|
ecc_data[i/4] >>= 13;
|
|
}
|
|
|
|
num_err = (readl(®s->bank_regs[bank].sts) >> 10) & 0xF;
|
|
|
|
if (num_err == 0xF)
|
|
return -EBADMSG;
|
|
|
|
i = 0;
|
|
while (num_err--) {
|
|
change_bit(0, (unsigned long *)&err_idx[i]);
|
|
change_bit(1, (unsigned long *)&err_idx[i]);
|
|
|
|
if (err_idx[i] <= 512 * 8) {
|
|
change_bit(err_idx[i], (unsigned long *)dat);
|
|
i++;
|
|
}
|
|
}
|
|
return i;
|
|
}
|
|
|
|
/*
|
|
* fsmc_nand_probe - Probe function
|
|
* @pdev: platform device structure
|
|
*/
|
|
static int __init fsmc_nand_probe(struct platform_device *pdev)
|
|
{
|
|
struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
|
struct fsmc_nand_data *host;
|
|
struct mtd_info *mtd;
|
|
struct nand_chip *nand;
|
|
struct fsmc_regs *regs;
|
|
struct resource *res;
|
|
int ret = 0;
|
|
u32 pid;
|
|
int i;
|
|
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "platform data is NULL\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Allocate memory for the device structure (and zero it) */
|
|
host = kzalloc(sizeof(*host), GFP_KERNEL);
|
|
if (!host) {
|
|
dev_err(&pdev->dev, "failed to allocate device structure\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
|
|
if (!res) {
|
|
ret = -EIO;
|
|
goto err_probe1;
|
|
}
|
|
|
|
host->resdata = request_mem_region(res->start, resource_size(res),
|
|
pdev->name);
|
|
if (!host->resdata) {
|
|
ret = -EIO;
|
|
goto err_probe1;
|
|
}
|
|
|
|
host->data_va = ioremap(res->start, resource_size(res));
|
|
if (!host->data_va) {
|
|
ret = -EIO;
|
|
goto err_probe1;
|
|
}
|
|
|
|
host->resaddr = request_mem_region(res->start + PLAT_NAND_ALE,
|
|
resource_size(res), pdev->name);
|
|
if (!host->resaddr) {
|
|
ret = -EIO;
|
|
goto err_probe1;
|
|
}
|
|
|
|
host->addr_va = ioremap(res->start + PLAT_NAND_ALE, resource_size(res));
|
|
if (!host->addr_va) {
|
|
ret = -EIO;
|
|
goto err_probe1;
|
|
}
|
|
|
|
host->rescmd = request_mem_region(res->start + PLAT_NAND_CLE,
|
|
resource_size(res), pdev->name);
|
|
if (!host->rescmd) {
|
|
ret = -EIO;
|
|
goto err_probe1;
|
|
}
|
|
|
|
host->cmd_va = ioremap(res->start + PLAT_NAND_CLE, resource_size(res));
|
|
if (!host->cmd_va) {
|
|
ret = -EIO;
|
|
goto err_probe1;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
|
|
if (!res) {
|
|
ret = -EIO;
|
|
goto err_probe1;
|
|
}
|
|
|
|
host->resregs = request_mem_region(res->start, resource_size(res),
|
|
pdev->name);
|
|
if (!host->resregs) {
|
|
ret = -EIO;
|
|
goto err_probe1;
|
|
}
|
|
|
|
host->regs_va = ioremap(res->start, resource_size(res));
|
|
if (!host->regs_va) {
|
|
ret = -EIO;
|
|
goto err_probe1;
|
|
}
|
|
|
|
host->clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(host->clk)) {
|
|
dev_err(&pdev->dev, "failed to fetch block clock\n");
|
|
ret = PTR_ERR(host->clk);
|
|
host->clk = NULL;
|
|
goto err_probe1;
|
|
}
|
|
|
|
ret = clk_enable(host->clk);
|
|
if (ret)
|
|
goto err_probe1;
|
|
|
|
/*
|
|
* This device ID is actually a common AMBA ID as used on the
|
|
* AMBA PrimeCell bus. However it is not a PrimeCell.
|
|
*/
|
|
for (pid = 0, i = 0; i < 4; i++)
|
|
pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
|
|
host->pid = pid;
|
|
dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
|
|
"revision %02x, config %02x\n",
|
|
AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
|
|
AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
|
|
|
|
host->bank = pdata->bank;
|
|
host->select_chip = pdata->select_bank;
|
|
regs = host->regs_va;
|
|
|
|
/* Link all private pointers */
|
|
mtd = &host->mtd;
|
|
nand = &host->nand;
|
|
mtd->priv = nand;
|
|
nand->priv = host;
|
|
|
|
host->mtd.owner = THIS_MODULE;
|
|
nand->IO_ADDR_R = host->data_va;
|
|
nand->IO_ADDR_W = host->data_va;
|
|
nand->cmd_ctrl = fsmc_cmd_ctrl;
|
|
nand->chip_delay = 30;
|
|
|
|
nand->ecc.mode = NAND_ECC_HW;
|
|
nand->ecc.hwctl = fsmc_enable_hwecc;
|
|
nand->ecc.size = 512;
|
|
nand->options = pdata->options;
|
|
nand->select_chip = fsmc_select_chip;
|
|
|
|
if (pdata->width == FSMC_NAND_BW16)
|
|
nand->options |= NAND_BUSWIDTH_16;
|
|
|
|
fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16);
|
|
|
|
if (AMBA_REV_BITS(host->pid) >= 8) {
|
|
nand->ecc.read_page = fsmc_read_page_hwecc;
|
|
nand->ecc.calculate = fsmc_read_hwecc_ecc4;
|
|
nand->ecc.correct = fsmc_correct_data;
|
|
nand->ecc.bytes = 13;
|
|
} else {
|
|
nand->ecc.calculate = fsmc_read_hwecc_ecc1;
|
|
nand->ecc.correct = nand_correct_data;
|
|
nand->ecc.bytes = 3;
|
|
}
|
|
|
|
/*
|
|
* Scan to find existance of the device
|
|
*/
|
|
if (nand_scan_ident(&host->mtd, 1, NULL)) {
|
|
ret = -ENXIO;
|
|
dev_err(&pdev->dev, "No NAND Device found!\n");
|
|
goto err_probe;
|
|
}
|
|
|
|
if (AMBA_REV_BITS(host->pid) >= 8) {
|
|
if (host->mtd.writesize == 512) {
|
|
nand->ecc.layout = &fsmc_ecc4_sp_layout;
|
|
host->ecc_place = &fsmc_ecc4_sp_place;
|
|
} else {
|
|
nand->ecc.layout = &fsmc_ecc4_lp_layout;
|
|
host->ecc_place = &fsmc_ecc4_lp_place;
|
|
}
|
|
} else {
|
|
nand->ecc.layout = &fsmc_ecc1_layout;
|
|
}
|
|
|
|
/* Second stage of scan to fill MTD data-structures */
|
|
if (nand_scan_tail(&host->mtd)) {
|
|
ret = -ENXIO;
|
|
goto err_probe;
|
|
}
|
|
|
|
/*
|
|
* The partition information can is accessed by (in the same precedence)
|
|
*
|
|
* command line through Bootloader,
|
|
* platform data,
|
|
* default partition information present in driver.
|
|
*/
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
#ifdef CONFIG_MTD_CMDLINE_PARTS
|
|
/*
|
|
* Check if partition info passed via command line
|
|
*/
|
|
host->mtd.name = "nand";
|
|
host->nr_partitions = parse_mtd_partitions(&host->mtd, part_probes,
|
|
&host->partitions, 0);
|
|
if (host->nr_partitions <= 0) {
|
|
#endif
|
|
/*
|
|
* Check if partition info passed via command line
|
|
*/
|
|
if (pdata->partitions) {
|
|
host->partitions = pdata->partitions;
|
|
host->nr_partitions = pdata->nr_partitions;
|
|
} else {
|
|
struct mtd_partition *partition;
|
|
int i;
|
|
|
|
/* Select the default partitions info */
|
|
switch (host->mtd.size) {
|
|
case 0x01000000:
|
|
case 0x02000000:
|
|
case 0x04000000:
|
|
host->partitions = partition_info_16KB_blk;
|
|
host->nr_partitions =
|
|
sizeof(partition_info_16KB_blk) /
|
|
sizeof(struct mtd_partition);
|
|
break;
|
|
case 0x08000000:
|
|
case 0x10000000:
|
|
case 0x20000000:
|
|
case 0x40000000:
|
|
host->partitions = partition_info_128KB_blk;
|
|
host->nr_partitions =
|
|
sizeof(partition_info_128KB_blk) /
|
|
sizeof(struct mtd_partition);
|
|
break;
|
|
default:
|
|
ret = -ENXIO;
|
|
pr_err("Unsupported NAND size\n");
|
|
goto err_probe;
|
|
}
|
|
|
|
partition = host->partitions;
|
|
for (i = 0; i < host->nr_partitions; i++, partition++) {
|
|
if (partition->size == 0) {
|
|
partition->size = host->mtd.size -
|
|
partition->offset;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
#ifdef CONFIG_MTD_CMDLINE_PARTS
|
|
}
|
|
#endif
|
|
|
|
if (host->partitions) {
|
|
ret = add_mtd_partitions(&host->mtd, host->partitions,
|
|
host->nr_partitions);
|
|
if (ret)
|
|
goto err_probe;
|
|
}
|
|
#else
|
|
dev_info(&pdev->dev, "Registering %s as whole device\n", mtd->name);
|
|
if (!add_mtd_device(mtd)) {
|
|
ret = -ENXIO;
|
|
goto err_probe;
|
|
}
|
|
#endif
|
|
|
|
platform_set_drvdata(pdev, host);
|
|
dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
|
|
return 0;
|
|
|
|
err_probe:
|
|
clk_disable(host->clk);
|
|
err_probe1:
|
|
if (host->clk)
|
|
clk_put(host->clk);
|
|
if (host->regs_va)
|
|
iounmap(host->regs_va);
|
|
if (host->resregs)
|
|
release_mem_region(host->resregs->start,
|
|
resource_size(host->resregs));
|
|
if (host->cmd_va)
|
|
iounmap(host->cmd_va);
|
|
if (host->rescmd)
|
|
release_mem_region(host->rescmd->start,
|
|
resource_size(host->rescmd));
|
|
if (host->addr_va)
|
|
iounmap(host->addr_va);
|
|
if (host->resaddr)
|
|
release_mem_region(host->resaddr->start,
|
|
resource_size(host->resaddr));
|
|
if (host->data_va)
|
|
iounmap(host->data_va);
|
|
if (host->resdata)
|
|
release_mem_region(host->resdata->start,
|
|
resource_size(host->resdata));
|
|
|
|
kfree(host);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Clean up routine
|
|
*/
|
|
static int fsmc_nand_remove(struct platform_device *pdev)
|
|
{
|
|
struct fsmc_nand_data *host = platform_get_drvdata(pdev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
if (host) {
|
|
#ifdef CONFIG_MTD_PARTITIONS
|
|
del_mtd_partitions(&host->mtd);
|
|
#else
|
|
del_mtd_device(&host->mtd);
|
|
#endif
|
|
clk_disable(host->clk);
|
|
clk_put(host->clk);
|
|
|
|
iounmap(host->regs_va);
|
|
release_mem_region(host->resregs->start,
|
|
resource_size(host->resregs));
|
|
iounmap(host->cmd_va);
|
|
release_mem_region(host->rescmd->start,
|
|
resource_size(host->rescmd));
|
|
iounmap(host->addr_va);
|
|
release_mem_region(host->resaddr->start,
|
|
resource_size(host->resaddr));
|
|
iounmap(host->data_va);
|
|
release_mem_region(host->resdata->start,
|
|
resource_size(host->resdata));
|
|
|
|
kfree(host);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int fsmc_nand_suspend(struct device *dev)
|
|
{
|
|
struct fsmc_nand_data *host = dev_get_drvdata(dev);
|
|
if (host)
|
|
clk_disable(host->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int fsmc_nand_resume(struct device *dev)
|
|
{
|
|
struct fsmc_nand_data *host = dev_get_drvdata(dev);
|
|
if (host)
|
|
clk_enable(host->clk);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops fsmc_nand_pm_ops = {
|
|
.suspend = fsmc_nand_suspend,
|
|
.resume = fsmc_nand_resume,
|
|
};
|
|
#endif
|
|
|
|
static struct platform_driver fsmc_nand_driver = {
|
|
.remove = fsmc_nand_remove,
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = "fsmc-nand",
|
|
#ifdef CONFIG_PM
|
|
.pm = &fsmc_nand_pm_ops,
|
|
#endif
|
|
},
|
|
};
|
|
|
|
static int __init fsmc_nand_init(void)
|
|
{
|
|
return platform_driver_probe(&fsmc_nand_driver,
|
|
fsmc_nand_probe);
|
|
}
|
|
module_init(fsmc_nand_init);
|
|
|
|
static void __exit fsmc_nand_exit(void)
|
|
{
|
|
platform_driver_unregister(&fsmc_nand_driver);
|
|
}
|
|
module_exit(fsmc_nand_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
|
|
MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
|