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The Cadence MIPI-CSI2 TX controller is an hardware block meant to be used as a bridge between pixel interfaces and a CSI-2 bus. It supports operating with an internal or external D-PHY, with up to 4 lanes, or without any D-PHY. The current code only supports the latter case. While the virtual channel input on the pixel interface can be directly mapped to CSI2, the datatype input is actually a selection signal (3-bits) mapping to a table of up to 8 preconfigured datatypes/formats (programmed at start-up) The block supports up to 8 input datatypes. Acked-by: Benoit Parrot <bparrot@ti.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
5 lines
140 B
Makefile
5 lines
140 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_VIDEO_CADENCE_CSI2RX) += cdns-csi2rx.o
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obj-$(CONFIG_VIDEO_CADENCE_CSI2TX) += cdns-csi2tx.o
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