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linux/drivers/gpu/drm/msm/dsi
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Hai Li 328e1a633c drm/msm/dsi: Save/Restore PLL status across PHY reset 
Reset DSI PHY silently changes its PLL registers to reset status,
which will make cached status in clock driver invalid and result
in wrong output rate of link clocks. The current restore mechanism
in DSI PLL does not cover all the cases. This change is to recover
PLL status after PHY reset to match HW status with cached status
in clock driver.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-08-15 18:27:18 -04:00
..
pll drm/msm/dsi: Save/Restore PLL status across PHY reset 2015-08-15 18:27:18 -04:00
dsi_host.c drm/msm/dsi: Report PHY errors only when they really occur 2015-08-15 18:27:14 -04:00
dsi_manager.c drm/msm/dsi: Save/Restore PLL status across PHY reset 2015-08-15 18:27:18 -04:00
dsi_phy.c drm/msm/dsi: Add support for msm8x94 2015-08-15 18:27:12 -04:00
dsi.c drm/msm/dsi: One function call less in dsi_init() after error detection 2015-08-15 18:27:17 -04:00
dsi.h drm/msm/dsi: Save/Restore PLL status across PHY reset 2015-08-15 18:27:18 -04:00
dsi.xml.h drm/msm: update generated headers 2015-08-15 18:27:10 -04:00
mmss_cc.xml.h drm/msm: update generated headers 2015-08-15 18:27:10 -04:00
sfpb.xml.h drm/msm: update generated headers 2015-08-15 18:27:10 -04:00