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cdb647a772
Originally mtk-sysirq hardcoded supported irq number to 224. This was fine since all SoCs before support the same number of irqs for intpol. However MT8173 intpol support 32 more irq pins, changes to get irq number from register resource size to suppor MT8173 properly. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Cc: <srv_heupstream@mediatek.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Olof Johansson <olof@lixom.net> Cc: Robert Richter <rrichter@cavium.com> Cc: Mark Brown <broonie@linaro.org> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: <marc.zyngier@arm.com> Cc: <peter.maydell@linaro.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1421054073-43468-3-git-send-email-eddie.huang@mediatek.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
168 lines
4.3 KiB
C
168 lines
4.3 KiB
C
/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Joe.C <yingjoe.chen@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "irqchip.h"
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struct mtk_sysirq_chip_data {
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spinlock_t lock;
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void __iomem *intpol_base;
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};
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static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
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{
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irq_hw_number_t hwirq = data->hwirq;
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struct mtk_sysirq_chip_data *chip_data = data->chip_data;
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u32 offset, reg_index, value;
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unsigned long flags;
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int ret;
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offset = hwirq & 0x1f;
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reg_index = hwirq >> 5;
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spin_lock_irqsave(&chip_data->lock, flags);
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value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
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if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
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if (type == IRQ_TYPE_LEVEL_LOW)
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type = IRQ_TYPE_LEVEL_HIGH;
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else
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type = IRQ_TYPE_EDGE_RISING;
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value |= (1 << offset);
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} else {
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value &= ~(1 << offset);
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}
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writel(value, chip_data->intpol_base + reg_index * 4);
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data = data->parent_data;
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ret = data->chip->irq_set_type(data, type);
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spin_unlock_irqrestore(&chip_data->lock, flags);
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return ret;
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}
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static struct irq_chip mtk_sysirq_chip = {
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.name = "MT_SYSIRQ",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_type = mtk_sysirq_set_type,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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};
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static int mtk_sysirq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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if (intsize != 3)
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return -EINVAL;
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/* sysirq doesn't support PPI */
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if (intspec[0])
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return -EINVAL;
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*out_hwirq = intspec[1];
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*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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int i;
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irq_hw_number_t hwirq;
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struct of_phandle_args *irq_data = arg;
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struct of_phandle_args gic_data = *irq_data;
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if (irq_data->args_count != 3)
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return -EINVAL;
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/* sysirq doesn't support PPI */
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if (irq_data->args[0])
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return -EINVAL;
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hwirq = irq_data->args[1];
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
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&mtk_sysirq_chip,
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domain->host_data);
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gic_data.np = domain->parent->of_node;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
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}
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static struct irq_domain_ops sysirq_domain_ops = {
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.xlate = mtk_sysirq_domain_xlate,
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.alloc = mtk_sysirq_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int __init mtk_sysirq_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *domain, *domain_parent;
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struct mtk_sysirq_chip_data *chip_data;
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int ret, size, intpol_num;
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struct resource res;
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domain_parent = irq_find_host(parent);
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if (!domain_parent) {
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pr_err("mtk_sysirq: interrupt-parent not found\n");
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return -EINVAL;
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}
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ret = of_address_to_resource(node, 0, &res);
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if (ret)
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return ret;
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chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
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if (!chip_data)
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return -ENOMEM;
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size = resource_size(&res);
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intpol_num = size * 8;
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chip_data->intpol_base = ioremap(res.start, size);
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if (!chip_data->intpol_base) {
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pr_err("mtk_sysirq: unable to map sysirq register\n");
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ret = PTR_ERR(chip_data->intpol_base);
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goto out_free;
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}
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domain = irq_domain_add_hierarchy(domain_parent, 0, intpol_num, node,
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&sysirq_domain_ops, chip_data);
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if (!domain) {
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ret = -ENOMEM;
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goto out_unmap;
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}
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spin_lock_init(&chip_data->lock);
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return 0;
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out_unmap:
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iounmap(chip_data->intpol_base);
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out_free:
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kfree(chip_data);
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return ret;
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}
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IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);
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