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Based on the normalized pattern: this program is free software you may redistribute it and/or modify it under the terms of the gnu general public license as published by the free software foundation version 2 of the license the software is provided as is without warranty of any kind express or implied including but not limited to the warranties of merchantability fitness for a particular purpose and noninfringement in no event shall the authors or copyright holders be liable for any claim damages or other liability whether in an action of contract tort or otherwise arising from out of or in connection with the software or the use or other dealings in the software extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
181 lines
4.4 KiB
C
181 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright 2014 Cisco Systems, Inc. All rights reserved.
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include "vnic_dev.h"
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#include "vnic_intr.h"
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#include "vnic_stats.h"
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#include "snic_io.h"
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#include "snic.h"
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/*
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* snic_isr_msix_wq : MSIx ISR for work queue.
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*/
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static irqreturn_t
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snic_isr_msix_wq(int irq, void *data)
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{
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struct snic *snic = data;
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unsigned long wq_work_done = 0;
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snic->s_stats.misc.last_isr_time = jiffies;
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atomic64_inc(&snic->s_stats.misc.ack_isr_cnt);
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wq_work_done = snic_wq_cmpl_handler(snic, -1);
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svnic_intr_return_credits(&snic->intr[SNIC_MSIX_WQ],
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wq_work_done,
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1 /* unmask intr */,
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1 /* reset intr timer */);
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return IRQ_HANDLED;
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} /* end of snic_isr_msix_wq */
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static irqreturn_t
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snic_isr_msix_io_cmpl(int irq, void *data)
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{
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struct snic *snic = data;
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unsigned long iocmpl_work_done = 0;
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snic->s_stats.misc.last_isr_time = jiffies;
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atomic64_inc(&snic->s_stats.misc.cmpl_isr_cnt);
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iocmpl_work_done = snic_fwcq_cmpl_handler(snic, -1);
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svnic_intr_return_credits(&snic->intr[SNIC_MSIX_IO_CMPL],
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iocmpl_work_done,
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1 /* unmask intr */,
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1 /* reset intr timer */);
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return IRQ_HANDLED;
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} /* end of snic_isr_msix_io_cmpl */
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static irqreturn_t
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snic_isr_msix_err_notify(int irq, void *data)
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{
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struct snic *snic = data;
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snic->s_stats.misc.last_isr_time = jiffies;
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atomic64_inc(&snic->s_stats.misc.errnotify_isr_cnt);
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svnic_intr_return_all_credits(&snic->intr[SNIC_MSIX_ERR_NOTIFY]);
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snic_log_q_error(snic);
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/*Handling link events */
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snic_handle_link_event(snic);
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return IRQ_HANDLED;
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} /* end of snic_isr_msix_err_notify */
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void
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snic_free_intr(struct snic *snic)
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{
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int i;
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/* ONLY interrupt mode MSIX is supported */
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for (i = 0; i < ARRAY_SIZE(snic->msix); i++) {
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if (snic->msix[i].requested) {
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free_irq(pci_irq_vector(snic->pdev, i),
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snic->msix[i].devid);
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}
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}
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} /* end of snic_free_intr */
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int
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snic_request_intr(struct snic *snic)
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{
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int ret = 0, i;
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enum vnic_dev_intr_mode intr_mode;
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intr_mode = svnic_dev_get_intr_mode(snic->vdev);
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SNIC_BUG_ON(intr_mode != VNIC_DEV_INTR_MODE_MSIX);
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/*
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* Currently HW supports single WQ and CQ. So passing devid as snic.
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* When hardware supports multiple WQs and CQs, one idea is
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* to pass devid as corresponding WQ or CQ ptr and retrieve snic
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* from queue ptr.
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* Except for err_notify, which is always one.
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*/
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sprintf(snic->msix[SNIC_MSIX_WQ].devname,
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"%.11s-scsi-wq",
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snic->name);
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snic->msix[SNIC_MSIX_WQ].isr = snic_isr_msix_wq;
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snic->msix[SNIC_MSIX_WQ].devid = snic;
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sprintf(snic->msix[SNIC_MSIX_IO_CMPL].devname,
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"%.11s-io-cmpl",
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snic->name);
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snic->msix[SNIC_MSIX_IO_CMPL].isr = snic_isr_msix_io_cmpl;
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snic->msix[SNIC_MSIX_IO_CMPL].devid = snic;
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sprintf(snic->msix[SNIC_MSIX_ERR_NOTIFY].devname,
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"%.11s-err-notify",
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snic->name);
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snic->msix[SNIC_MSIX_ERR_NOTIFY].isr = snic_isr_msix_err_notify;
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snic->msix[SNIC_MSIX_ERR_NOTIFY].devid = snic;
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for (i = 0; i < ARRAY_SIZE(snic->msix); i++) {
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ret = request_irq(pci_irq_vector(snic->pdev, i),
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snic->msix[i].isr,
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0,
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snic->msix[i].devname,
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snic->msix[i].devid);
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if (ret) {
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SNIC_HOST_ERR(snic->shost,
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"MSI-X: request_irq(%d) failed %d\n",
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i,
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ret);
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snic_free_intr(snic);
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break;
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}
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snic->msix[i].requested = 1;
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}
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return ret;
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} /* end of snic_request_intr */
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int
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snic_set_intr_mode(struct snic *snic)
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{
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unsigned int n = ARRAY_SIZE(snic->wq);
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unsigned int m = SNIC_CQ_IO_CMPL_MAX;
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unsigned int vecs = n + m + 1;
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/*
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* We need n WQs, m CQs, and n+m+1 INTRs
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* (last INTR is used for WQ/CQ errors and notification area
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*/
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BUILD_BUG_ON((ARRAY_SIZE(snic->wq) + SNIC_CQ_IO_CMPL_MAX) >
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ARRAY_SIZE(snic->intr));
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if (snic->wq_count < n || snic->cq_count < n + m)
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goto fail;
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if (pci_alloc_irq_vectors(snic->pdev, vecs, vecs, PCI_IRQ_MSIX) < 0)
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goto fail;
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snic->wq_count = n;
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snic->cq_count = n + m;
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snic->intr_count = vecs;
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snic->err_intr_offset = SNIC_MSIX_ERR_NOTIFY;
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SNIC_ISR_DBG(snic->shost, "Using MSI-X Interrupts\n");
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svnic_dev_set_intr_mode(snic->vdev, VNIC_DEV_INTR_MODE_MSIX);
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return 0;
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fail:
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svnic_dev_set_intr_mode(snic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
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return -EINVAL;
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} /* end of snic_set_intr_mode */
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void
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snic_clear_intr_mode(struct snic *snic)
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{
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pci_free_irq_vectors(snic->pdev);
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svnic_dev_set_intr_mode(snic->vdev, VNIC_DEV_INTR_MODE_INTX);
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}
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