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ec3eb9d941
Currently the perf CPU backend drivers detect what CPU they're on using cur_cpu_spec->oprofile_cpu_type. Although that works, it's a bit crufty to be using oprofile related fields, especially seeing as oprofile is more or less unused these days. It also means perf is reliant on the fragile logic in setup_cpu_spec() which detects when we're using a logical PVR and copies back the PMU related fields from the raw CPU entry. So lets check the PVR directly. Suggested-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> [chleroy: Added power10 and fixed checkpatch issues] Reviewed-and-tested-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Reviewed-and-tested-By: Kajol Jain <kjain@linux.ibm.com> [For 24x7 side changes] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20c0ee7f99dbf0dbf8658df6b39f84753e6db1ef.1657204631.git.christophe.leroy@csgroup.eu
429 lines
10 KiB
C
429 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Performance counter support for MPC7450-family processors.
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*
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
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*/
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#include <linux/string.h>
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#include <linux/perf_event.h>
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#include <asm/reg.h>
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#include <asm/cputable.h>
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#define N_COUNTER 6 /* Number of hardware counters */
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#define MAX_ALT 3 /* Maximum number of event alternative codes */
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/*
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* Bits in event code for MPC7450 family
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*/
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#define PM_THRMULT_MSKS 0x40000
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#define PM_THRESH_SH 12
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#define PM_THRESH_MSK 0x3f
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#define PM_PMC_SH 8
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#define PM_PMC_MSK 7
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#define PM_PMCSEL_MSK 0x7f
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/*
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* Classify events according to how specific their PMC requirements are.
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* Result is:
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* 0: can go on any PMC
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* 1: can go on PMCs 1-4
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* 2: can go on PMCs 1,2,4
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* 3: can go on PMCs 1 or 2
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* 4: can only go on one PMC
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* -1: event code is invalid
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*/
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#define N_CLASSES 5
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static int mpc7450_classify_event(u32 event)
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{
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int pmc;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc > N_COUNTER)
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return -1;
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return 4;
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}
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event &= PM_PMCSEL_MSK;
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if (event <= 1)
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return 0;
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if (event <= 7)
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return 1;
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if (event <= 13)
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return 2;
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if (event <= 22)
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return 3;
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return -1;
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}
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/*
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* Events using threshold and possible threshold scale:
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* code scale? name
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* 11e N PM_INSTQ_EXCEED_CYC
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* 11f N PM_ALTV_IQ_EXCEED_CYC
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* 128 Y PM_DTLB_SEARCH_EXCEED_CYC
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* 12b Y PM_LD_MISS_EXCEED_L1_CYC
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* 220 N PM_CQ_EXCEED_CYC
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* 30c N PM_GPR_RB_EXCEED_CYC
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* 30d ? PM_FPR_IQ_EXCEED_CYC ?
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* 311 Y PM_ITLB_SEARCH_EXCEED
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* 410 N PM_GPR_IQ_EXCEED_CYC
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*/
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/*
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* Return use of threshold and threshold scale bits:
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* 0 = uses neither, 1 = uses threshold, 2 = uses both
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*/
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static int mpc7450_threshold_use(u32 event)
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{
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int pmc, sel;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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sel = event & PM_PMCSEL_MSK;
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switch (pmc) {
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case 1:
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if (sel == 0x1e || sel == 0x1f)
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return 1;
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if (sel == 0x28 || sel == 0x2b)
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return 2;
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break;
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case 2:
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if (sel == 0x20)
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return 1;
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break;
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case 3:
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if (sel == 0xc || sel == 0xd)
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return 1;
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if (sel == 0x11)
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return 2;
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break;
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case 4:
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if (sel == 0x10)
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return 1;
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break;
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}
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return 0;
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}
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/*
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* Layout of constraint bits:
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* 33222222222211111111110000000000
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* 10987654321098765432109876543210
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* |< >< > < > < ><><><><><><>
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* TS TV G4 G3 G2P6P5P4P3P2P1
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*
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* P1 - P6
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* 0 - 11: Count of events needing PMC1 .. PMC6
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*
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* G2
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* 12 - 14: Count of events needing PMC1 or PMC2
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*
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* G3
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* 16 - 18: Count of events needing PMC1, PMC2 or PMC4
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*
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* G4
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* 20 - 23: Count of events needing PMC1, PMC2, PMC3 or PMC4
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*
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* TV
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* 24 - 29: Threshold value requested
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*
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* TS
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* 30: Threshold scale value requested
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*/
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static u32 pmcbits[N_COUNTER][2] = {
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{ 0x00844002, 0x00111001 }, /* PMC1 mask, value: P1,G2,G3,G4 */
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{ 0x00844008, 0x00111004 }, /* PMC2: P2,G2,G3,G4 */
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{ 0x00800020, 0x00100010 }, /* PMC3: P3,G4 */
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{ 0x00840080, 0x00110040 }, /* PMC4: P4,G3,G4 */
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{ 0x00000200, 0x00000100 }, /* PMC5: P5 */
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{ 0x00000800, 0x00000400 } /* PMC6: P6 */
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};
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static u32 classbits[N_CLASSES - 1][2] = {
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{ 0x00000000, 0x00000000 }, /* class 0: no constraint */
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{ 0x00800000, 0x00100000 }, /* class 1: G4 */
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{ 0x00040000, 0x00010000 }, /* class 2: G3 */
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{ 0x00004000, 0x00001000 }, /* class 3: G2 */
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};
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static int mpc7450_get_constraint(u64 event, unsigned long *maskp,
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unsigned long *valp, u64 event_config1 __maybe_unused)
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{
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int pmc, class;
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u32 mask, value;
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int thresh, tuse;
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class = mpc7450_classify_event(event);
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if (class < 0)
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return -1;
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if (class == 4) {
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pmc = ((unsigned int)event >> PM_PMC_SH) & PM_PMC_MSK;
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mask = pmcbits[pmc - 1][0];
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value = pmcbits[pmc - 1][1];
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} else {
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mask = classbits[class][0];
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value = classbits[class][1];
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}
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tuse = mpc7450_threshold_use(event);
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if (tuse) {
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thresh = ((unsigned int)event >> PM_THRESH_SH) & PM_THRESH_MSK;
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mask |= 0x3f << 24;
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value |= thresh << 24;
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if (tuse == 2) {
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mask |= 0x40000000;
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if ((unsigned int)event & PM_THRMULT_MSKS)
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value |= 0x40000000;
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}
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}
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*maskp = mask;
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*valp = value;
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return 0;
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}
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static const unsigned int event_alternatives[][MAX_ALT] = {
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{ 0x217, 0x317 }, /* PM_L1_DCACHE_MISS */
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{ 0x418, 0x50f, 0x60f }, /* PM_SNOOP_RETRY */
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{ 0x502, 0x602 }, /* PM_L2_HIT */
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{ 0x503, 0x603 }, /* PM_L3_HIT */
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{ 0x504, 0x604 }, /* PM_L2_ICACHE_MISS */
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{ 0x505, 0x605 }, /* PM_L3_ICACHE_MISS */
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{ 0x506, 0x606 }, /* PM_L2_DCACHE_MISS */
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{ 0x507, 0x607 }, /* PM_L3_DCACHE_MISS */
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{ 0x50a, 0x623 }, /* PM_LD_HIT_L3 */
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{ 0x50b, 0x624 }, /* PM_ST_HIT_L3 */
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{ 0x50d, 0x60d }, /* PM_L2_TOUCH_HIT */
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{ 0x50e, 0x60e }, /* PM_L3_TOUCH_HIT */
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{ 0x512, 0x612 }, /* PM_INT_LOCAL */
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{ 0x513, 0x61d }, /* PM_L2_MISS */
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{ 0x514, 0x61e }, /* PM_L3_MISS */
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};
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/*
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* Scan the alternatives table for a match and return the
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* index into the alternatives table if found, else -1.
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*/
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static int find_alternative(u32 event)
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{
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int i, j;
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for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
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if (event < event_alternatives[i][0])
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break;
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for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
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if (event == event_alternatives[i][j])
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return i;
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}
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return -1;
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}
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static int mpc7450_get_alternatives(u64 event, unsigned int flags, u64 alt[])
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{
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int i, j, nalt = 1;
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u32 ae;
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alt[0] = event;
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nalt = 1;
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i = find_alternative((u32)event);
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if (i >= 0) {
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for (j = 0; j < MAX_ALT; ++j) {
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ae = event_alternatives[i][j];
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if (ae && ae != (u32)event)
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alt[nalt++] = ae;
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}
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}
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return nalt;
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}
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/*
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* Bitmaps of which PMCs each class can use for classes 0 - 3.
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* Bit i is set if PMC i+1 is usable.
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*/
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static const u8 classmap[N_CLASSES] = {
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0x3f, 0x0f, 0x0b, 0x03, 0
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};
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/* Bit position and width of each PMCSEL field */
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static const int pmcsel_shift[N_COUNTER] = {
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6, 0, 27, 22, 17, 11
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};
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static const u32 pmcsel_mask[N_COUNTER] = {
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0x7f, 0x3f, 0x1f, 0x1f, 0x1f, 0x3f
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};
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/*
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* Compute MMCR0/1/2 values for a set of events.
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*/
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static int mpc7450_compute_mmcr(u64 event[], int n_ev, unsigned int hwc[],
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struct mmcr_regs *mmcr,
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struct perf_event *pevents[],
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u32 flags __maybe_unused)
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{
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u8 event_index[N_CLASSES][N_COUNTER];
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int n_classevent[N_CLASSES];
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int i, j, class, tuse;
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u32 pmc_inuse = 0, pmc_avail;
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u32 mmcr0 = 0, mmcr1 = 0, mmcr2 = 0;
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u32 ev, pmc, thresh;
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if (n_ev > N_COUNTER)
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return -1;
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/* First pass: count usage in each class */
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for (i = 0; i < N_CLASSES; ++i)
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n_classevent[i] = 0;
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for (i = 0; i < n_ev; ++i) {
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class = mpc7450_classify_event(event[i]);
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if (class < 0)
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return -1;
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j = n_classevent[class]++;
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event_index[class][j] = i;
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}
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/* Second pass: allocate PMCs from most specific event to least */
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for (class = N_CLASSES - 1; class >= 0; --class) {
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for (i = 0; i < n_classevent[class]; ++i) {
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ev = event[event_index[class][i]];
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if (class == 4) {
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pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc_inuse & (1 << (pmc - 1)))
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return -1;
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} else {
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/* Find a suitable PMC */
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pmc_avail = classmap[class] & ~pmc_inuse;
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if (!pmc_avail)
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return -1;
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pmc = ffs(pmc_avail);
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}
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pmc_inuse |= 1 << (pmc - 1);
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tuse = mpc7450_threshold_use(ev);
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if (tuse) {
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thresh = (ev >> PM_THRESH_SH) & PM_THRESH_MSK;
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mmcr0 |= thresh << 16;
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if (tuse == 2 && (ev & PM_THRMULT_MSKS))
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mmcr2 = 0x80000000;
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}
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ev &= pmcsel_mask[pmc - 1];
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ev <<= pmcsel_shift[pmc - 1];
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if (pmc <= 2)
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mmcr0 |= ev;
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else
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mmcr1 |= ev;
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hwc[event_index[class][i]] = pmc - 1;
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}
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}
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if (pmc_inuse & 1)
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mmcr0 |= MMCR0_PMC1CE;
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if (pmc_inuse & 0x3e)
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mmcr0 |= MMCR0_PMCnCE;
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/* Return MMCRx values */
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mmcr->mmcr0 = mmcr0;
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mmcr->mmcr1 = mmcr1;
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mmcr->mmcr2 = mmcr2;
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/*
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* 32-bit doesn't have an MMCRA and uses SPRN_MMCR2 to define
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* SPRN_MMCRA. So assign mmcra of cpu_hw_events with `mmcr2`
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* value to ensure that any write to this SPRN_MMCRA will
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* use mmcr2 value.
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*/
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mmcr->mmcra = mmcr2;
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return 0;
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}
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/*
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* Disable counting by a PMC.
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* Note that the pmc argument is 0-based here, not 1-based.
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*/
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static void mpc7450_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
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{
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if (pmc <= 1)
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mmcr->mmcr0 &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
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else
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mmcr->mmcr1 &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
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}
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static int mpc7450_generic_events[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = 1,
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[PERF_COUNT_HW_INSTRUCTIONS] = 2,
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[PERF_COUNT_HW_CACHE_MISSES] = 0x217, /* PM_L1_DCACHE_MISS */
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x122, /* PM_BR_CMPL */
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x41c, /* PM_BR_MPRED */
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};
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#define C(x) PERF_COUNT_HW_CACHE_##x
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/*
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* Table of generalized cache-related events.
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* 0 means not supported, -1 means nonsensical, other values
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* are event codes.
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*/
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static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x225 },
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[C(OP_WRITE)] = { 0, 0x227 },
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[C(OP_PREFETCH)] = { 0, 0 },
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},
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[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x129, 0x115 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { 0x634, 0 },
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},
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[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0 },
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[C(OP_WRITE)] = { 0, 0 },
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[C(OP_PREFETCH)] = { 0, 0 },
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},
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[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x312 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x223 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x122, 0x41c },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { -1, -1 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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};
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struct power_pmu mpc7450_pmu = {
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.name = "MPC7450 family",
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.n_counter = N_COUNTER,
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.max_alternatives = MAX_ALT,
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.add_fields = 0x00111555ul,
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.test_adder = 0x00301000ul,
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.compute_mmcr = mpc7450_compute_mmcr,
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.get_constraint = mpc7450_get_constraint,
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.get_alternatives = mpc7450_get_alternatives,
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.disable_pmc = mpc7450_disable_pmc,
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.n_generic = ARRAY_SIZE(mpc7450_generic_events),
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.generic_events = mpc7450_generic_events,
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.cache_events = &mpc7450_cache_events,
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};
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static int __init init_mpc7450_pmu(void)
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{
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unsigned int pvr = mfspr(SPRN_PVR);
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if (PVR_VER(pvr) != PVR_7450)
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return -ENODEV;
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return register_power_pmu(&mpc7450_pmu);
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}
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early_initcall(init_mpc7450_pmu);
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