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c4d06d2d20
Add port management message for setting Rx mode in the card, used for rx_mode netdev operation. The link event handler is used for getting a notification about the link state. Signed-off-by: Aviad Krawczyk <aviad.krawczyk@huawei.com> Signed-off-by: Zhao Chen <zhaochen6@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
316 lines
9.1 KiB
C
316 lines
9.1 KiB
C
/*
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* Huawei HiNIC PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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*/
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#include <linux/pci.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include "hinic_hw_csr.h"
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#include "hinic_hw_if.h"
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#define PCIE_ATTR_ENTRY 0
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#define VALID_MSIX_IDX(attr, msix_index) ((msix_index) < (attr)->num_irqs)
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/**
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* hinic_msix_attr_set - set message attribute for msix entry
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* @hwif: the HW interface of a pci function device
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* @msix_index: msix_index
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* @pending_limit: the maximum pending interrupt events (unit 8)
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* @coalesc_timer: coalesc period for interrupt (unit 8 us)
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* @lli_timer: replenishing period for low latency credit (unit 8 us)
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* @lli_credit_limit: maximum credits for low latency msix messages (unit 8)
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* @resend_timer: maximum wait for resending msix (unit coalesc period)
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*
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* Return 0 - Success, negative - Failure
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**/
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int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,
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u8 pending_limit, u8 coalesc_timer,
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u8 lli_timer, u8 lli_credit_limit,
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u8 resend_timer)
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{
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u32 msix_ctrl, addr;
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if (!VALID_MSIX_IDX(&hwif->attr, msix_index))
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return -EINVAL;
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msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) |
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HINIC_MSIX_ATTR_SET(coalesc_timer, COALESC_TIMER) |
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HINIC_MSIX_ATTR_SET(lli_timer, LLI_TIMER) |
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HINIC_MSIX_ATTR_SET(lli_credit_limit, LLI_CREDIT) |
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HINIC_MSIX_ATTR_SET(resend_timer, RESEND_TIMER);
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addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index);
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hinic_hwif_write_reg(hwif, addr, msix_ctrl);
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return 0;
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}
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/**
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* hinic_msix_attr_get - get message attribute of msix entry
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* @hwif: the HW interface of a pci function device
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* @msix_index: msix_index
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* @pending_limit: the maximum pending interrupt events (unit 8)
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* @coalesc_timer: coalesc period for interrupt (unit 8 us)
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* @lli_timer: replenishing period for low latency credit (unit 8 us)
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* @lli_credit_limit: maximum credits for low latency msix messages (unit 8)
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* @resend_timer: maximum wait for resending msix (unit coalesc period)
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*
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* Return 0 - Success, negative - Failure
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**/
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int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index,
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u8 *pending_limit, u8 *coalesc_timer,
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u8 *lli_timer, u8 *lli_credit_limit,
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u8 *resend_timer)
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{
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u32 addr, val;
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if (!VALID_MSIX_IDX(&hwif->attr, msix_index))
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return -EINVAL;
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addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index);
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val = hinic_hwif_read_reg(hwif, addr);
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*pending_limit = HINIC_MSIX_ATTR_GET(val, PENDING_LIMIT);
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*coalesc_timer = HINIC_MSIX_ATTR_GET(val, COALESC_TIMER);
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*lli_timer = HINIC_MSIX_ATTR_GET(val, LLI_TIMER);
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*lli_credit_limit = HINIC_MSIX_ATTR_GET(val, LLI_CREDIT);
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*resend_timer = HINIC_MSIX_ATTR_GET(val, RESEND_TIMER);
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return 0;
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}
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/**
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* hinic_msix_attr_cnt_clear - clear message attribute counters for msix entry
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* @hwif: the HW interface of a pci function device
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* @msix_index: msix_index
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*
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* Return 0 - Success, negative - Failure
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**/
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int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index)
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{
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u32 msix_ctrl, addr;
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if (!VALID_MSIX_IDX(&hwif->attr, msix_index))
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return -EINVAL;
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msix_ctrl = HINIC_MSIX_CNT_SET(1, RESEND_TIMER);
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addr = HINIC_CSR_MSIX_CNT_ADDR(msix_index);
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hinic_hwif_write_reg(hwif, addr, msix_ctrl);
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return 0;
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}
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/**
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* hinic_set_pf_action - set action on pf channel
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* @hwif: the HW interface of a pci function device
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* @action: action on pf channel
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*
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* Return 0 - Success, negative - Failure
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**/
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void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action)
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{
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u32 attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR);
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attr5 = HINIC_FA5_CLEAR(attr5, PF_ACTION);
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attr5 |= HINIC_FA5_SET(action, PF_ACTION);
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hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR, attr5);
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}
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/**
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* hwif_ready - test if the HW is ready for use
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* @hwif: the HW interface of a pci function device
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*
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* Return 0 - Success, negative - Failure
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**/
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static int hwif_ready(struct hinic_hwif *hwif)
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{
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struct pci_dev *pdev = hwif->pdev;
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u32 addr, attr1;
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addr = HINIC_CSR_FUNC_ATTR1_ADDR;
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attr1 = hinic_hwif_read_reg(hwif, addr);
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if (!HINIC_FA1_GET(attr1, INIT_STATUS)) {
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dev_err(&pdev->dev, "hwif status is not ready\n");
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return -EFAULT;
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}
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return 0;
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}
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/**
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* set_hwif_attr - set the attributes in the relevant members in hwif
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* @hwif: the HW interface of a pci function device
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* @attr0: the first attribute that was read from the hw
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* @attr1: the second attribute that was read from the hw
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**/
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static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1)
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{
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hwif->attr.func_idx = HINIC_FA0_GET(attr0, FUNC_IDX);
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hwif->attr.pf_idx = HINIC_FA0_GET(attr0, PF_IDX);
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hwif->attr.pci_intf_idx = HINIC_FA0_GET(attr0, PCI_INTF_IDX);
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hwif->attr.func_type = HINIC_FA0_GET(attr0, FUNC_TYPE);
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hwif->attr.num_aeqs = BIT(HINIC_FA1_GET(attr1, AEQS_PER_FUNC));
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hwif->attr.num_ceqs = BIT(HINIC_FA1_GET(attr1, CEQS_PER_FUNC));
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hwif->attr.num_irqs = BIT(HINIC_FA1_GET(attr1, IRQS_PER_FUNC));
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hwif->attr.num_dma_attr = BIT(HINIC_FA1_GET(attr1, DMA_ATTR_PER_FUNC));
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}
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/**
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* read_hwif_attr - read the attributes and set members in hwif
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* @hwif: the HW interface of a pci function device
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**/
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static void read_hwif_attr(struct hinic_hwif *hwif)
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{
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u32 addr, attr0, attr1;
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addr = HINIC_CSR_FUNC_ATTR0_ADDR;
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attr0 = hinic_hwif_read_reg(hwif, addr);
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addr = HINIC_CSR_FUNC_ATTR1_ADDR;
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attr1 = hinic_hwif_read_reg(hwif, addr);
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set_hwif_attr(hwif, attr0, attr1);
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}
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/**
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* set_ppf - try to set hwif as ppf and set the type of hwif in this case
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* @hwif: the HW interface of a pci function device
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**/
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static void set_ppf(struct hinic_hwif *hwif)
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{
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struct hinic_func_attr *attr = &hwif->attr;
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u32 addr, val, ppf_election;
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/* Read Modify Write */
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addr = HINIC_CSR_PPF_ELECTION_ADDR(HINIC_HWIF_PCI_INTF(hwif));
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val = hinic_hwif_read_reg(hwif, addr);
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val = HINIC_PPF_ELECTION_CLEAR(val, IDX);
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ppf_election = HINIC_PPF_ELECTION_SET(HINIC_HWIF_FUNC_IDX(hwif), IDX);
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val |= ppf_election;
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hinic_hwif_write_reg(hwif, addr, val);
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/* check PPF */
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val = hinic_hwif_read_reg(hwif, addr);
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attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX);
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if (attr->ppf_idx == HINIC_HWIF_FUNC_IDX(hwif))
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attr->func_type = HINIC_PPF;
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}
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/**
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* set_dma_attr - set the dma attributes in the HW
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* @hwif: the HW interface of a pci function device
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* @entry_idx: the entry index in the dma table
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* @st: PCIE TLP steering tag
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* @at: PCIE TLP AT field
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* @ph: PCIE TLP Processing Hint field
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* @no_snooping: PCIE TLP No snooping
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* @tph_en: PCIE TLP Processing Hint Enable
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**/
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static void set_dma_attr(struct hinic_hwif *hwif, u32 entry_idx,
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u8 st, u8 at, u8 ph,
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enum hinic_pcie_nosnoop no_snooping,
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enum hinic_pcie_tph tph_en)
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{
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u32 addr, val, dma_attr_entry;
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/* Read Modify Write */
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addr = HINIC_CSR_DMA_ATTR_ADDR(entry_idx);
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val = hinic_hwif_read_reg(hwif, addr);
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val = HINIC_DMA_ATTR_CLEAR(val, ST) &
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HINIC_DMA_ATTR_CLEAR(val, AT) &
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HINIC_DMA_ATTR_CLEAR(val, PH) &
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HINIC_DMA_ATTR_CLEAR(val, NO_SNOOPING) &
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HINIC_DMA_ATTR_CLEAR(val, TPH_EN);
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dma_attr_entry = HINIC_DMA_ATTR_SET(st, ST) |
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HINIC_DMA_ATTR_SET(at, AT) |
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HINIC_DMA_ATTR_SET(ph, PH) |
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HINIC_DMA_ATTR_SET(no_snooping, NO_SNOOPING) |
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HINIC_DMA_ATTR_SET(tph_en, TPH_EN);
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val |= dma_attr_entry;
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hinic_hwif_write_reg(hwif, addr, val);
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}
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/**
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* dma_attr_table_init - initialize the the default dma attributes
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* @hwif: the HW interface of a pci function device
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**/
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static void dma_attr_init(struct hinic_hwif *hwif)
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{
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set_dma_attr(hwif, PCIE_ATTR_ENTRY, HINIC_PCIE_ST_DISABLE,
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HINIC_PCIE_AT_DISABLE, HINIC_PCIE_PH_DISABLE,
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HINIC_PCIE_SNOOP, HINIC_PCIE_TPH_DISABLE);
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}
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/**
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* hinic_init_hwif - initialize the hw interface
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* @hwif: the HW interface of a pci function device
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* @pdev: the pci device for acessing PCI resources
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*
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* Return 0 - Success, negative - Failure
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**/
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int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev)
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{
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int err;
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hwif->pdev = pdev;
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hwif->cfg_regs_bar = pci_ioremap_bar(pdev, HINIC_PCI_CFG_REGS_BAR);
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if (!hwif->cfg_regs_bar) {
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dev_err(&pdev->dev, "Failed to map configuration regs\n");
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return -ENOMEM;
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}
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err = hwif_ready(hwif);
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if (err) {
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dev_err(&pdev->dev, "HW interface is not ready\n");
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goto err_hwif_ready;
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}
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read_hwif_attr(hwif);
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if (HINIC_IS_PF(hwif))
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set_ppf(hwif);
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/* No transactionss before DMA is initialized */
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dma_attr_init(hwif);
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return 0;
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err_hwif_ready:
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iounmap(hwif->cfg_regs_bar);
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return err;
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}
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/**
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* hinic_free_hwif - free the HW interface
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* @hwif: the HW interface of a pci function device
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**/
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void hinic_free_hwif(struct hinic_hwif *hwif)
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{
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iounmap(hwif->cfg_regs_bar);
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}
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