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6054d4d563
This patch enable writing nand flash via NFC SRAM. It will minimize the CPU overhead. The SRAM write only support ECC_NONE and ECC_HW with PMECC. To enable this NFC write by SRAM feature, you can add a string in dts under NFC driver node. This driver has been tested on SAMA5D3X-EK with JFFS2, YAFFS2, UBIFS and mtd-utils. Here is part of mtd_speedtest (writing test) result, compare with non-NFC writing, it reduces %65 cpu load with loss %12 speed. - commands use to test: # insmod /mnt/mtd_speedtest.ko dev=2 & # top -n 30 -d 1 | grep speedtest - test result: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64 mtd_speedtest: testing eraseblock write speed 509 495 root D 1164 0% 7% insmod /mnt/mtd_speedtest.ko dev=2 509 495 root D 1164 0% 8% insmod /mnt/mtd_speedtest.ko dev=2 509 495 root R 1164 0% 5% insmod /mnt/mtd_speedtest.ko dev=2 mtd_speedtest: eraseblock write speed is 5194 KiB/s mtd_speedtest: testing page write speed 509 495 root D 1164 0% 32% insmod /mnt/mtd_speedtest.ko dev=2 509 495 root D 1164 0% 27% insmod /mnt/mtd_speedtest.ko dev=2 509 495 root D 1164 0% 25% insmod /mnt/mtd_speedtest.ko dev=2 509 495 root D 1164 0% 30% insmod /mnt/mtd_speedtest.ko dev=2 mtd_speedtest: page write speed is 5024 KiB/s Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
108 lines
3.5 KiB
Plaintext
108 lines
3.5 KiB
Plaintext
Atmel NAND flash
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Required properties:
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- compatible : "atmel,at91rm9200-nand".
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- reg : should specify localbus address and size used for the chip,
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and hardware ECC controller if available.
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If the hardware ECC is PMECC, it should contain address and size for
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PMECC, PMECC Error Location controller and ROM which has lookup tables.
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- atmel,nand-addr-offset : offset for the address latch.
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- atmel,nand-cmd-offset : offset for the command latch.
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- #address-cells, #size-cells : Must be present if the device has sub-nodes
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representing partitions.
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- gpios : specifies the gpio pins to control the NAND device. detect is an
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optional gpio and may be set to 0 if not present.
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Optional properties:
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- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
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- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
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Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
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"soft_bch".
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- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware.
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Only supported by at91sam9x5 or later sam9 product.
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- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
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Controller. Supported values are: 2, 4, 8, 12, 24.
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- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
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are: 512, 1024.
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- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
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for different sector size. First one is for sector size 512, the next is for
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sector size 1024.
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- nand-bus-width : 8 or 16 bus width if not present 8
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- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
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- Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
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- Required properties:
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- compatible : "atmel,sama5d3-nfc".
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- reg : should specify the address and size used for NFC command registers,
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NFC registers and NFC Sram. NFC Sram address and size can be absent
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if don't want to use it.
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- Optional properties:
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- atmel,write-by-sram: boolean to enable NFC write by sram.
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Examples:
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nand0: nand@40000000,0 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40000000 0x10000000
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0xffffe800 0x200
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>;
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atmel,nand-addr-offset = <21>; /* ale */
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atmel,nand-cmd-offset = <22>; /* cle */
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nand-on-flash-bbt;
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nand-ecc-mode = "soft";
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gpios = <&pioC 13 0 /* rdy */
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&pioC 14 0 /* nce */
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0 /* cd */
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>;
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partition@0 {
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...
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};
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};
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/* for PMECC supported chips */
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nand0: nand@40000000 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = < 0x40000000 0x10000000 /* bus addr & size */
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0xffffe000 0x00000600 /* PMECC addr & size */
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0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */
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0x00100000 0x00100000 /* ROM addr & size */
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>;
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atmel,nand-addr-offset = <21>; /* ale */
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atmel,nand-cmd-offset = <22>; /* cle */
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nand-on-flash-bbt;
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nand-ecc-mode = "hw";
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atmel,has-pmecc; /* enable PMECC */
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atmel,pmecc-cap = <2>;
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atmel,pmecc-sector-size = <512>;
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atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
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gpios = <&pioD 5 0 /* rdy */
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&pioD 4 0 /* nce */
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0 /* cd */
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>;
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partition@0 {
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...
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};
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};
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/* for NFC supported chips */
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nand0: nand@40000000 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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...
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nfc@70000000 {
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compatible = "atmel,sama5d3-nfc";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <
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0x70000000 0x10000000 /* NFC Command Registers */
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0xffffc000 0x00000070 /* NFC HSMC regs */
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0x00200000 0x00100000 /* NFC SRAM banks */
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>;
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};
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};
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