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76062b4ae2
This patch adds a new API to indicate S0ix residency in usec. It utilizes
the PMC Global Control Registers (GCR) to read deep and shallow
S0ix residency.
PMC MMIO resources:
o Lower 4kB: IPC1 (PMC inter-processor communication) interface
o Upper 4kB: GCR (Global Control Registers)
This enables the power management framework to take corrective actions when
the platform fails to enter S0ix after kernel freeze as part of the suspend
to idle flow. (echo freeze > /sys/power/state).
This is expected to be used with a S0ix failsafe framework such as:
<https://lwn.net/Articles/689505/>
[rajneesh: folded in "fix division in 32-bit case" from Andy Shevchenko]
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: Shanth Murthy <shanth.murthy@intel.com>
[andy: fixed kbuild error, removed "total" from variables, fixed macro]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
62 lines
1.5 KiB
C
62 lines
1.5 KiB
C
#ifndef _ASM_X86_INTEL_PMC_IPC_H_
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#define _ASM_X86_INTEL_PMC_IPC_H_
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/* Commands */
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#define PMC_IPC_PMIC_ACCESS 0xFF
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#define PMC_IPC_PMIC_ACCESS_READ 0x0
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#define PMC_IPC_PMIC_ACCESS_WRITE 0x1
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#define PMC_IPC_USB_PWR_CTRL 0xF0
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#define PMC_IPC_PMIC_BLACKLIST_SEL 0xEF
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#define PMC_IPC_PHY_CONFIG 0xEE
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#define PMC_IPC_NORTHPEAK_CTRL 0xED
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#define PMC_IPC_PM_DEBUG 0xEC
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#define PMC_IPC_PMC_TELEMTRY 0xEB
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#define PMC_IPC_PMC_FW_MSG_CTRL 0xEA
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/* IPC return code */
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#define IPC_ERR_NONE 0
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#define IPC_ERR_CMD_NOT_SUPPORTED 1
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#define IPC_ERR_CMD_NOT_SERVICED 2
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#define IPC_ERR_UNABLE_TO_SERVICE 3
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#define IPC_ERR_CMD_INVALID 4
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#define IPC_ERR_CMD_FAILED 5
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#define IPC_ERR_EMSECURITY 6
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#define IPC_ERR_UNSIGNEDKERNEL 7
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#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
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int intel_pmc_ipc_simple_command(int cmd, int sub);
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int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
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u32 *out, u32 outlen, u32 dptr, u32 sptr);
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int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
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u32 *out, u32 outlen);
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int intel_pmc_s0ix_counter_read(u64 *data);
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#else
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static inline int intel_pmc_ipc_simple_command(int cmd, int sub)
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{
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return -EINVAL;
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}
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static inline int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
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u32 *out, u32 outlen, u32 dptr, u32 sptr)
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{
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return -EINVAL;
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}
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static inline int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
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u32 *out, u32 outlen)
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{
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return -EINVAL;
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}
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static inline int intel_pmc_s0ix_counter_read(u64 *data)
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{
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return -EINVAL;
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}
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#endif /*CONFIG_INTEL_PMC_IPC*/
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#endif
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