James Liao 75ce0cdb62 clk: mediatek: Add MT8173 MMPLL change rate support ... MT8173 MMPLL frequency settings are different from common PLLs. It needs different post divider settings for some ranges of frequency. This patch add support for MT8173 MMPLL frequency setting by adding div-rate table to lookup suitable post divider setting under a specified frequency. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2015-07-28 11:58:57 -07:00
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clk-gate.c	clk: mediatek: Initialize clk_init_data	2015-05-19 18:40:48 -07:00
clk-gate.h
clk-mt8135.c	clk: mediatek: Fix apmixedsys clock registration	2015-06-04 14:07:07 -07:00
clk-mt8173.c	clk: mediatek: Add MT8173 MMPLL change rate support	2015-07-28 11:58:57 -07:00
clk-mtk.c
clk-mtk.h	clk: mediatek: Add MT8173 MMPLL change rate support	2015-07-28 11:58:57 -07:00
clk-pll.c	clk: mediatek: Add MT8173 MMPLL change rate support	2015-07-28 11:58:57 -07:00
Makefile	clk: mediatek: Add basic clocks for Mediatek MT8173.	2015-05-05 22:50:38 -07:00
reset.c