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cdaea91019
Add the reset binding documentation to the SoC binding documentation as the reset driver in Marvell Berlin SoC is part of the chip/system control registers. This patch adds the required properties to configure the reset controller. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
153 lines
4.7 KiB
Plaintext
153 lines
4.7 KiB
Plaintext
Marvell Berlin SoC Family Device Tree Bindings
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---------------------------------------------------------------
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Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
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shall have the following properties:
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* Required root node properties:
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compatible: must contain "marvell,berlin"
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In addition, the above compatible shall be extended with the specific
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SoC and board used. Currently known SoC compatibles are:
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"marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
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"marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
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"marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
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"marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
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"marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
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* Example:
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/ {
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model = "Sony NSZ-GS7";
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compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
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...
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}
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* Marvell Berlin CPU control bindings
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CPU control register allows various operations on CPUs, like resetting them
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independently.
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Required properties:
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- compatible: should be "marvell,berlin-cpu-ctrl"
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- reg: address and length of the register set
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Example:
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cpu-ctrl@f7dd0000 {
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compatible = "marvell,berlin-cpu-ctrl";
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reg = <0xf7dd0000 0x10000>;
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};
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* Marvell Berlin2 chip control binding
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Marvell Berlin SoCs have a chip control register set providing several
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individual registers dealing with pinmux, padmux, clock, reset, and secondary
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CPU boot address. Unfortunately, the individual registers are spread among the
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chip control registers, so there should be a single DT node only providing the
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different functions which are described below.
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Required properties:
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- compatible: shall be one of
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"marvell,berlin2-chip-ctrl" for BG2
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"marvell,berlin2cd-chip-ctrl" for BG2CD
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"marvell,berlin2q-chip-ctrl" for BG2Q
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- reg: address and length of following register sets for
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BG2/BG2CD: chip control register set
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BG2Q: chip control register set and cpu pll registers
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* Marvell Berlin2 system control binding
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Marvell Berlin SoCs have a system control register set providing several
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individual registers dealing with pinmux, padmux, and reset.
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Required properties:
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- compatible: should be one of
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"marvell,berlin2-system-ctrl" for BG2
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"marvell,berlin2cd-system-ctrl" for BG2CD
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"marvell,berlin2q-system-ctrl" for BG2Q
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- reg: address and length of the system control register set
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* Clock provider binding
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As clock related registers are spread among the chip control registers, the
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chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
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SoCs share the same IP for PLLs and clocks, with some minor differences in
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features and register layout.
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Required properties:
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- #clock-cells: shall be set to 1
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- clocks: clock specifiers referencing the core clock input clocks
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- clock-names: array of strings describing the input clock specifiers above.
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Allowed clock-names for the reference clocks are
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"refclk" for the SoCs osciallator input on all SoCs,
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and SoC-specific input clocks for
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BG2/BG2CD: "video_ext0" for the external video clock input
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Clocks provided by core clocks shall be referenced by a clock specifier
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indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
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for the corresponding index mapping.
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* Pin controller binding
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Pin control registers are part of both register sets, chip control and system
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control. The pins controlled are organized in groups, so no actual pin
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information is needed.
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A pin-controller node should contain subnodes representing the pin group
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configurations, one per function. Each subnode has the group name and the muxing
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function used.
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Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
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a 'function' in the pin-controller subsystem.
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Required subnode-properties:
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- groups: a list of strings describing the group names.
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- function: a string describing the function used to mux the groups.
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* Reset controller binding
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A reset controller is part of the chip control registers set. The chip control
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node also provides the reset. The register set is not at the same offset between
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Berlin SoCs.
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Required property:
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- #reset-cells: must be set to 2
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Example:
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chip: chip-control@ea0000 {
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compatible = "marvell,berlin2-chip-ctrl";
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#clock-cells = <1>;
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#reset-cells = <2>;
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reg = <0xea0000 0x400>;
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clocks = <&refclk>, <&externaldev 0>;
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clock-names = "refclk", "video_ext0";
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spi1_pmux: spi1-pmux {
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groups = "G0";
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function = "spi1";
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};
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};
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sysctrl: system-controller@d000 {
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compatible = "marvell,berlin2-system-ctrl";
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reg = <0xd000 0x100>;
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uart0_pmux: uart0-pmux {
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groups = "GSM4";
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function = "uart0";
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};
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uart1_pmux: uart1-pmux {
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groups = "GSM5";
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function = "uart1";
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};
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uart2_pmux: uart2-pmux {
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groups = "GSM3";
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function = "uart2";
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};
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};
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