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'interrupt-parent' is often documented as part of define bindings, but it is really outside the scope of a device binding. It's never required in a given node as it is often inherited from a parent node. Or it can be implicit if a parent node is an 'interrupt-controller' node. So remove it from all the binding files. Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
132 lines
2.7 KiB
Plaintext
132 lines
2.7 KiB
Plaintext
BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
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The BCM2835 contains a custom top-level interrupt controller, which supports
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72 interrupt sources using a 2-level register scheme. The interrupt
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controller, or the HW block containing it, is referred to occasionally
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as "armctrl" in the SoC documentation, hence naming of this binding.
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The BCM2836 contains the same interrupt controller with the same
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interrupts, but the per-CPU interrupt controller is the root, and an
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interrupt there indicates that the ARMCTRL has an interrupt to handle.
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Required properties:
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- compatible : should be "brcm,bcm2835-armctrl-ic" or
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"brcm,bcm2836-armctrl-ic"
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- reg : Specifies base physical address and size of the registers.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 2.
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The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
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pending" register, or 1/2 respectively for interrupts in the "IRQ pending
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1/2" register.
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The 2nd cell contains the interrupt number within the bank. Valid values
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are 0..7 for bank 0, and 0..31 for bank 1.
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Additional required properties for brcm,bcm2836-armctrl-ic:
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- interrupts : Specifies the interrupt on the parent for this interrupt
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controller to handle.
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The interrupt sources are as follows:
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Bank 0:
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0: ARM_TIMER
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1: ARM_MAILBOX
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2: ARM_DOORBELL_0
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3: ARM_DOORBELL_1
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4: VPU0_HALTED
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5: VPU1_HALTED
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6: ILLEGAL_TYPE0
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7: ILLEGAL_TYPE1
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Bank 1:
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0: TIMER0
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1: TIMER1
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2: TIMER2
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3: TIMER3
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4: CODEC0
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5: CODEC1
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6: CODEC2
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7: VC_JPEG
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8: ISP
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9: VC_USB
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10: VC_3D
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11: TRANSPOSER
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12: MULTICORESYNC0
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13: MULTICORESYNC1
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14: MULTICORESYNC2
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15: MULTICORESYNC3
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16: DMA0
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17: DMA1
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18: VC_DMA2
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19: VC_DMA3
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20: DMA4
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21: DMA5
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22: DMA6
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23: DMA7
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24: DMA8
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25: DMA9
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26: DMA10
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27: DMA11-14 - shared interrupt for DMA 11 to 14
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28: DMAALL - triggers on all dma interrupts (including chanel 15)
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29: AUX
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30: ARM
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31: VPUDMA
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Bank 2:
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0: HOSTPORT
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1: VIDEOSCALER
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2: CCP2TX
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3: SDC
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4: DSI0
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5: AVE
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6: CAM0
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7: CAM1
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8: HDMI0
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9: HDMI1
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10: PIXELVALVE1
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11: I2CSPISLV
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12: DSI1
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13: PWA0
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14: PWA1
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15: CPR
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16: SMI
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17: GPIO0
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18: GPIO1
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19: GPIO2
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20: GPIO3
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21: VC_I2C
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22: VC_SPI
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23: VC_I2SPCM
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24: VC_SDIO
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25: VC_UART
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26: SLIMBUS
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27: VEC
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28: CPG
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29: RNG
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30: VC_ARASANSDIO
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31: AVSPMON
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Example:
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/* BCM2835, first level */
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intc: interrupt-controller {
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compatible = "brcm,bcm2835-armctrl-ic";
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reg = <0x7e00b200 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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/* BCM2836, second level */
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intc: interrupt-controller {
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compatible = "brcm,bcm2836-armctrl-ic";
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reg = <0x7e00b200 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&local_intc>;
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interrupts = <8>;
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};
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