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8469cdef1f
Send a notification to the driver on succesful reception of an ADDBA response, add IEEE80211_AMPDU_TX_RESUME for this purpose. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
972 lines
30 KiB
C
972 lines
30 KiB
C
/*
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* Copyright (c) 2008 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef CORE_H
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#define CORE_H
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#include <linux/version.h>
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#include <linux/autoconf.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/ip.h>
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#include <linux/tcp.h>
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#include <linux/in.h>
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#include <linux/delay.h>
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#include <linux/wait.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/list.h>
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#include <asm/byteorder.h>
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#include <linux/scatterlist.h>
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#include <asm/page.h>
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#include <net/mac80211.h>
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#include <linux/leds.h>
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#include <linux/rfkill.h>
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#include "ath9k.h"
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#include "rc.h"
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struct ath_node;
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/******************/
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/* Utility macros */
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/******************/
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/* Macro to expand scalars to 64-bit objects */
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#define ito64(x) (sizeof(x) == 8) ? \
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(((unsigned long long int)(x)) & (0xff)) : \
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(sizeof(x) == 16) ? \
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(((unsigned long long int)(x)) & 0xffff) : \
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((sizeof(x) == 32) ? \
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(((unsigned long long int)(x)) & 0xffffffff) : \
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(unsigned long long int)(x))
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/* increment with wrap-around */
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#define INCR(_l, _sz) do { \
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(_l)++; \
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(_l) &= ((_sz) - 1); \
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} while (0)
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/* decrement with wrap-around */
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#define DECR(_l, _sz) do { \
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(_l)--; \
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(_l) &= ((_sz) - 1); \
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} while (0)
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#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
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#define ASSERT(exp) do { \
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if (unlikely(!(exp))) { \
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BUG(); \
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} \
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} while (0)
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#define TSF_TO_TU(_h,_l) \
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((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
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#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
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static inline unsigned long get_timestamp(void)
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{
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return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
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}
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static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
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/*************/
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/* Debugging */
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/*************/
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enum ATH_DEBUG {
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ATH_DBG_RESET = 0x00000001,
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ATH_DBG_PHY_IO = 0x00000002,
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ATH_DBG_REG_IO = 0x00000004,
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ATH_DBG_QUEUE = 0x00000008,
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ATH_DBG_EEPROM = 0x00000010,
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ATH_DBG_NF_CAL = 0x00000020,
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ATH_DBG_CALIBRATE = 0x00000040,
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ATH_DBG_CHANNEL = 0x00000080,
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ATH_DBG_INTERRUPT = 0x00000100,
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ATH_DBG_REGULATORY = 0x00000200,
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ATH_DBG_ANI = 0x00000400,
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ATH_DBG_POWER_MGMT = 0x00000800,
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ATH_DBG_XMIT = 0x00001000,
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ATH_DBG_BEACON = 0x00002000,
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ATH_DBG_RATE = 0x00004000,
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ATH_DBG_CONFIG = 0x00008000,
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ATH_DBG_KEYCACHE = 0x00010000,
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ATH_DBG_AGGR = 0x00020000,
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ATH_DBG_FATAL = 0x00040000,
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ATH_DBG_ANY = 0xffffffff
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};
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#define DBG_DEFAULT (ATH_DBG_FATAL)
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#define DPRINTF(sc, _m, _fmt, ...) do { \
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if (sc->sc_debug & (_m)) \
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printk(_fmt , ##__VA_ARGS__); \
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} while (0)
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/***************************/
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/* Load-time Configuration */
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/***************************/
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/* Per-instance load-time (note: NOT run-time) configurations
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* for Atheros Device */
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struct ath_config {
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u32 ath_aggr_prot;
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u16 txpowlimit;
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u16 txpowlimit_override;
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u8 cabqReadytime; /* Cabq Readytime % */
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u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
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};
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/***********************/
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/* Chainmask Selection */
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/***********************/
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#define ATH_CHAINMASK_SEL_TIMEOUT 6000
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/* Default - Number of last RSSI values that is used for
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* chainmask selection */
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#define ATH_CHAINMASK_SEL_RSSI_CNT 10
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/* Means use 3x3 chainmask instead of configured chainmask */
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#define ATH_CHAINMASK_SEL_3X3 7
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/* Default - Rssi threshold below which we have to switch to 3x3 */
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#define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
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/* Default - Rssi threshold above which we have to switch to
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* user configured values */
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#define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
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/* Struct to store the chainmask select related info */
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struct ath_chainmask_sel {
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struct timer_list timer;
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int cur_tx_mask; /* user configured or 3x3 */
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int cur_rx_mask; /* user configured or 3x3 */
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int tx_avgrssi;
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u8 switch_allowed:1, /* timer will set this */
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cm_sel_enabled : 1;
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};
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int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
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void ath_update_chainmask(struct ath_softc *sc, int is_ht);
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/*************************/
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/* Descriptor Management */
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/*************************/
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#define ATH_TXBUF_RESET(_bf) do { \
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(_bf)->bf_status = 0; \
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(_bf)->bf_lastbf = NULL; \
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(_bf)->bf_lastfrm = NULL; \
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(_bf)->bf_next = NULL; \
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memset(&((_bf)->bf_state), 0, \
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sizeof(struct ath_buf_state)); \
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} while (0)
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enum buffer_type {
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BUF_DATA = BIT(0),
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BUF_AGGR = BIT(1),
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BUF_AMPDU = BIT(2),
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BUF_HT = BIT(3),
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BUF_RETRY = BIT(4),
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BUF_XRETRY = BIT(5),
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BUF_SHORT_PREAMBLE = BIT(6),
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BUF_BAR = BIT(7),
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BUF_PSPOLL = BIT(8),
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BUF_AGGR_BURST = BIT(9),
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BUF_CALC_AIRTIME = BIT(10),
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};
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struct ath_buf_state {
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int bfs_nframes; /* # frames in aggregate */
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u16 bfs_al; /* length of aggregate */
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u16 bfs_frmlen; /* length of frame */
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int bfs_seqno; /* sequence number */
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int bfs_tidno; /* tid of this frame */
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int bfs_retries; /* current retries */
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struct ath_rc_series bfs_rcs[4]; /* rate series */
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u32 bf_type; /* BUF_* (enum buffer_type) */
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/* key type use to encrypt this frame */
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u32 bfs_keyix;
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enum ath9k_key_type bfs_keytype;
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};
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#define bf_nframes bf_state.bfs_nframes
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#define bf_al bf_state.bfs_al
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#define bf_frmlen bf_state.bfs_frmlen
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#define bf_retries bf_state.bfs_retries
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#define bf_seqno bf_state.bfs_seqno
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#define bf_tidno bf_state.bfs_tidno
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#define bf_rcs bf_state.bfs_rcs
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#define bf_keyix bf_state.bfs_keyix
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#define bf_keytype bf_state.bfs_keytype
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#define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
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#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
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#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
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#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
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#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
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#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
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#define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
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#define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
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#define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
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#define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
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/*
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* Abstraction of a contiguous buffer to transmit/receive. There is only
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* a single hw descriptor encapsulated here.
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*/
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struct ath_buf {
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struct list_head list;
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struct list_head *last;
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struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
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an aggregate) */
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struct ath_buf *bf_lastfrm; /* last buf of this frame */
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struct ath_buf *bf_next; /* next subframe in the aggregate */
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struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
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void *bf_mpdu; /* enclosing frame structure */
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struct ath_desc *bf_desc; /* virtual addr of desc */
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dma_addr_t bf_daddr; /* physical addr of desc */
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dma_addr_t bf_buf_addr; /* physical addr of data buffer */
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u32 bf_status;
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u16 bf_flags; /* tx descriptor flags */
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struct ath_buf_state bf_state; /* buffer state */
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dma_addr_t bf_dmacontext;
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};
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/*
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* reset the rx buffer.
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* any new fields added to the athbuf and require
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* reset need to be added to this macro.
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* currently bf_status is the only one requires that
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* requires reset.
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*/
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#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
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/* hw processing complete, desc processed by hal */
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#define ATH_BUFSTATUS_DONE 0x00000001
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/* hw processing complete, desc hold for hw */
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#define ATH_BUFSTATUS_STALE 0x00000002
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/* Rx-only: OS is done with this packet and it's ok to queued it to hw */
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#define ATH_BUFSTATUS_FREE 0x00000004
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/* DMA state for tx/rx descriptors */
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struct ath_descdma {
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const char *dd_name;
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struct ath_desc *dd_desc; /* descriptors */
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dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
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u32 dd_desc_len; /* size of dd_desc */
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struct ath_buf *dd_bufptr; /* associated buffers */
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dma_addr_t dd_dmacontext;
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};
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/* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
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struct ath_rx_context {
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struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */
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};
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#define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
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int ath_descdma_setup(struct ath_softc *sc,
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struct ath_descdma *dd,
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struct list_head *head,
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const char *name,
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int nbuf,
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int ndesc);
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int ath_desc_alloc(struct ath_softc *sc);
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void ath_desc_free(struct ath_softc *sc);
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void ath_descdma_cleanup(struct ath_softc *sc,
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struct ath_descdma *dd,
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struct list_head *head);
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/******/
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/* RX */
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/******/
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#define ATH_MAX_ANTENNA 3
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#define ATH_RXBUF 512
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#define WME_NUM_TID 16
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/* per frame rx status block */
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struct ath_recv_status {
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u64 tsf; /* mac tsf */
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int8_t rssi; /* RSSI (noise floor ajusted) */
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int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
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int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
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int8_t abs_rssi; /* absolute RSSI */
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u8 rateieee; /* data rate received (IEEE rate code) */
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u8 ratecode; /* phy rate code */
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int rateKbps; /* data rate received (Kbps) */
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int antenna; /* rx antenna */
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int flags; /* status of associated skb */
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#define ATH_RX_FCS_ERROR 0x01
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#define ATH_RX_MIC_ERROR 0x02
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#define ATH_RX_DECRYPT_ERROR 0x04
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#define ATH_RX_RSSI_VALID 0x08
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/* if any of ctl,extn chainrssis are valid */
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#define ATH_RX_CHAIN_RSSI_VALID 0x10
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/* if extn chain rssis are valid */
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#define ATH_RX_RSSI_EXTN_VALID 0x20
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/* set if 40Mhz, clear if 20Mhz */
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#define ATH_RX_40MHZ 0x40
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/* set if short GI, clear if full GI */
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#define ATH_RX_SHORT_GI 0x80
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};
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struct ath_rxbuf {
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struct sk_buff *rx_wbuf;
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unsigned long rx_time; /* system time when received */
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struct ath_recv_status rx_status; /* cached rx status */
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};
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int ath_startrecv(struct ath_softc *sc);
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bool ath_stoprecv(struct ath_softc *sc);
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void ath_flushrecv(struct ath_softc *sc);
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u32 ath_calcrxfilter(struct ath_softc *sc);
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void ath_handle_rx_intr(struct ath_softc *sc);
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int ath_rx_init(struct ath_softc *sc, int nbufs);
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void ath_rx_cleanup(struct ath_softc *sc);
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int ath_rx_tasklet(struct ath_softc *sc, int flush);
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int _ath_rx_indicate(struct ath_softc *sc,
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struct sk_buff *skb,
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struct ath_recv_status *status,
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u16 keyix);
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/******/
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/* TX */
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/******/
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#define ATH_TXBUF 512
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/* max number of transmit attempts (tries) */
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#define ATH_TXMAXTRY 13
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/* max number of 11n transmit attempts (tries) */
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#define ATH_11N_TXMAXTRY 10
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/* max number of tries for management and control frames */
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#define ATH_MGT_TXMAXTRY 4
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#define WME_BA_BMP_SIZE 64
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#define WME_MAX_BA WME_BA_BMP_SIZE
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#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
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#define TID_TO_WME_AC(_tid) \
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((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
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(((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
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(((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
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WME_AC_VO)
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/* Wireless Multimedia Extension Defines */
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#define WME_AC_BE 0 /* best effort */
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#define WME_AC_BK 1 /* background */
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#define WME_AC_VI 2 /* video */
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#define WME_AC_VO 3 /* voice */
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#define WME_NUM_AC 4
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/*
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* Data transmit queue state. One of these exists for each
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* hardware transmit queue. Packets sent to us from above
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* are assigned to queues based on their priority. Not all
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* devices support a complete set of hardware transmit queues.
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* For those devices the array sc_ac2q will map multiple
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* priorities to fewer hardware queues (typically all to one
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* hardware queue).
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*/
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struct ath_txq {
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u32 axq_qnum; /* hardware q number */
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u32 *axq_link; /* link ptr in last TX desc */
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struct list_head axq_q; /* transmit queue */
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spinlock_t axq_lock;
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unsigned long axq_lockflags; /* intr state when must cli */
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u32 axq_depth; /* queue depth */
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u8 axq_aggr_depth; /* aggregates queued */
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u32 axq_totalqueued; /* total ever queued */
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bool stopped; /* Is mac80211 queue stopped ? */
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struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
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/* first desc of the last descriptor that contains CTS */
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struct ath_desc *axq_lastdsWithCTS;
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/* final desc of the gating desc that determines whether
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lastdsWithCTS has been DMA'ed or not */
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struct ath_desc *axq_gatingds;
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struct list_head axq_acq;
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};
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#define AGGR_CLEANUP BIT(1)
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#define AGGR_ADDBA_COMPLETE BIT(2)
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#define AGGR_ADDBA_PROGRESS BIT(3)
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/* per TID aggregate tx state for a destination */
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struct ath_atx_tid {
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struct list_head list; /* round-robin tid entry */
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struct list_head buf_q; /* pending buffers */
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struct ath_node *an;
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struct ath_atx_ac *ac;
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struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
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u16 seq_start;
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u16 seq_next;
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u16 baw_size;
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int tidno;
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int baw_head; /* first un-acked tx buffer */
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int baw_tail; /* next unused tx buffer slot */
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int sched;
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int paused;
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u8 state;
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int addba_exchangeattempts;
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};
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/* per access-category aggregate tx state for a destination */
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struct ath_atx_ac {
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int sched; /* dest-ac is scheduled */
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int qnum; /* H/W queue number associated
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with this AC */
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struct list_head list; /* round-robin txq entry */
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struct list_head tid_q; /* queue of TIDs with buffers */
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};
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/* per dest tx state */
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struct ath_atx {
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struct ath_atx_tid tid[WME_NUM_TID];
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struct ath_atx_ac ac[WME_NUM_AC];
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};
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/* per-frame tx control block */
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struct ath_tx_control {
|
|
struct ath_txq *txq;
|
|
int if_id;
|
|
};
|
|
|
|
/* per frame tx status block */
|
|
struct ath_xmit_status {
|
|
int retries; /* number of retries to successufully
|
|
transmit this frame */
|
|
int flags; /* status of transmit */
|
|
#define ATH_TX_ERROR 0x01
|
|
#define ATH_TX_XRETRY 0x02
|
|
#define ATH_TX_BAR 0x04
|
|
};
|
|
|
|
struct ath_tx_stat {
|
|
int rssi; /* RSSI (noise floor ajusted) */
|
|
int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
|
|
int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
|
|
int rateieee; /* data rate xmitted (IEEE rate code) */
|
|
int rateKbps; /* data rate xmitted (Kbps) */
|
|
int ratecode; /* phy rate code */
|
|
int flags; /* validity flags */
|
|
/* if any of ctl,extn chain rssis are valid */
|
|
#define ATH_TX_CHAIN_RSSI_VALID 0x01
|
|
/* if extn chain rssis are valid */
|
|
#define ATH_TX_RSSI_EXTN_VALID 0x02
|
|
u32 airtime; /* time on air per final tx rate */
|
|
};
|
|
|
|
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
|
|
void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
|
|
int ath_tx_setup(struct ath_softc *sc, int haltype);
|
|
void ath_draintxq(struct ath_softc *sc, bool retry_tx);
|
|
void ath_tx_draintxq(struct ath_softc *sc,
|
|
struct ath_txq *txq, bool retry_tx);
|
|
void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
|
|
void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
|
|
void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
|
|
void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
|
|
int ath_tx_init(struct ath_softc *sc, int nbufs);
|
|
int ath_tx_cleanup(struct ath_softc *sc);
|
|
int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
|
|
struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
|
|
int ath_txq_update(struct ath_softc *sc, int qnum,
|
|
struct ath9k_tx_queue_info *q);
|
|
int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
|
|
struct ath_tx_control *txctl);
|
|
void ath_tx_tasklet(struct ath_softc *sc);
|
|
u32 ath_txq_depth(struct ath_softc *sc, int qnum);
|
|
u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
|
|
void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
|
|
void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
|
|
struct ath_xmit_status *tx_status);
|
|
void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
|
|
|
|
/**********************/
|
|
/* Node / Aggregation */
|
|
/**********************/
|
|
|
|
#define ADDBA_EXCHANGE_ATTEMPTS 10
|
|
#define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
|
|
#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
|
|
/* number of delimiters for encryption padding */
|
|
#define ATH_AGGR_ENCRYPTDELIM 10
|
|
/* minimum h/w qdepth to be sustained to maximize aggregation */
|
|
#define ATH_AGGR_MIN_QDEPTH 2
|
|
#define ATH_AMPDU_SUBFRAME_DEFAULT 32
|
|
#define IEEE80211_SEQ_SEQ_SHIFT 4
|
|
#define IEEE80211_SEQ_MAX 4096
|
|
#define IEEE80211_MIN_AMPDU_BUF 0x8
|
|
#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
|
|
|
|
/* return whether a bit at index _n in bitmap _bm is set
|
|
* _sz is the size of the bitmap */
|
|
#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
|
|
((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
|
|
|
|
/* return block-ack bitmap index given sequence and starting sequence */
|
|
#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
|
|
|
|
/* returns delimiter padding required given the packet length */
|
|
#define ATH_AGGR_GET_NDELIM(_len) \
|
|
(((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
|
|
(ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
|
|
|
|
#define BAW_WITHIN(_start, _bawsz, _seqno) \
|
|
((((_seqno) - (_start)) & 4095) < (_bawsz))
|
|
|
|
#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
|
|
#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
|
|
#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
|
|
#define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
|
|
|
|
enum ATH_AGGR_STATUS {
|
|
ATH_AGGR_DONE,
|
|
ATH_AGGR_BAW_CLOSED,
|
|
ATH_AGGR_LIMITED,
|
|
ATH_AGGR_SHORTPKT,
|
|
ATH_AGGR_8K_LIMITED,
|
|
};
|
|
|
|
struct aggr_rifs_param {
|
|
int param_max_frames;
|
|
int param_max_len;
|
|
int param_rl;
|
|
int param_al;
|
|
struct ath_rc_series *param_rcs;
|
|
};
|
|
|
|
/* Per-node aggregation state */
|
|
struct ath_node_aggr {
|
|
struct ath_atx tx; /* node transmit state */
|
|
};
|
|
|
|
/* driver-specific node state */
|
|
struct ath_node {
|
|
struct ath_softc *an_sc;
|
|
struct ath_chainmask_sel an_chainmask_sel;
|
|
struct ath_node_aggr an_aggr;
|
|
u16 maxampdu;
|
|
u8 mpdudensity;
|
|
};
|
|
|
|
void ath_tx_resume_tid(struct ath_softc *sc,
|
|
struct ath_atx_tid *tid);
|
|
bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
|
|
void ath_tx_aggr_teardown(struct ath_softc *sc,
|
|
struct ath_node *an, u8 tidno);
|
|
int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
|
|
u16 tid, u16 *ssn);
|
|
int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
|
|
void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
|
|
void ath_newassoc(struct ath_softc *sc,
|
|
struct ath_node *node, int isnew, int isuapsd);
|
|
void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta);
|
|
void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta);
|
|
|
|
/*******************/
|
|
/* Beacon Handling */
|
|
/*******************/
|
|
|
|
/*
|
|
* Regardless of the number of beacons we stagger, (i.e. regardless of the
|
|
* number of BSSIDs) if a given beacon does not go out even after waiting this
|
|
* number of beacon intervals, the game's up.
|
|
*/
|
|
#define BSTUCK_THRESH (9 * ATH_BCBUF)
|
|
#define ATH_BCBUF 4 /* number of beacon buffers */
|
|
#define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
|
|
#define ATH_DEFAULT_BMISS_LIMIT 10
|
|
#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
|
|
|
|
/* beacon configuration */
|
|
struct ath_beacon_config {
|
|
u16 beacon_interval;
|
|
u16 listen_interval;
|
|
u16 dtim_period;
|
|
u16 bmiss_timeout;
|
|
u8 dtim_count;
|
|
u8 tim_offset;
|
|
union {
|
|
u64 last_tsf;
|
|
u8 last_tstamp[8];
|
|
} u; /* last received beacon/probe response timestamp of this BSS. */
|
|
};
|
|
|
|
void ath9k_beacon_tasklet(unsigned long data);
|
|
void ath_beacon_config(struct ath_softc *sc, int if_id);
|
|
int ath_beaconq_setup(struct ath_hal *ah);
|
|
int ath_beacon_alloc(struct ath_softc *sc, int if_id);
|
|
void ath_bstuck_process(struct ath_softc *sc);
|
|
void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
|
|
void ath_beacon_sync(struct ath_softc *sc, int if_id);
|
|
void ath_get_beaconconfig(struct ath_softc *sc,
|
|
int if_id,
|
|
struct ath_beacon_config *conf);
|
|
/********/
|
|
/* VAPs */
|
|
/********/
|
|
|
|
/*
|
|
* Define the scheme that we select MAC address for multiple
|
|
* BSS on the same radio. The very first VAP will just use the MAC
|
|
* address from the EEPROM. For the next 3 VAPs, we set the
|
|
* U/L bit (bit 1) in MAC address, and use the next two bits as the
|
|
* index of the VAP.
|
|
*/
|
|
|
|
#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
|
|
((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
|
|
|
|
/* VAP configuration (from protocol layer) */
|
|
struct ath_vap_config {
|
|
u32 av_fixed_rateset;
|
|
u32 av_fixed_retryset;
|
|
};
|
|
|
|
/* driver-specific vap state */
|
|
struct ath_vap {
|
|
int av_bslot; /* beacon slot index */
|
|
enum ath9k_opmode av_opmode; /* VAP operational mode */
|
|
struct ath_buf *av_bcbuf; /* beacon buffer */
|
|
struct ath_tx_control av_btxctl; /* txctl information for beacon */
|
|
struct ath_vap_config av_config;/* vap configuration parameters*/
|
|
struct ath_rate_node *rc_node;
|
|
};
|
|
|
|
/*********************/
|
|
/* Antenna diversity */
|
|
/*********************/
|
|
|
|
#define ATH_ANT_DIV_MAX_CFG 2
|
|
#define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
|
|
#define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
|
|
|
|
enum ATH_ANT_DIV_STATE{
|
|
ATH_ANT_DIV_IDLE,
|
|
ATH_ANT_DIV_SCAN, /* evaluating antenna */
|
|
};
|
|
|
|
struct ath_antdiv {
|
|
struct ath_softc *antdiv_sc;
|
|
u8 antdiv_start;
|
|
enum ATH_ANT_DIV_STATE antdiv_state;
|
|
u8 antdiv_num_antcfg;
|
|
u8 antdiv_curcfg;
|
|
u8 antdiv_bestcfg;
|
|
int32_t antdivf_rssitrig;
|
|
int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
|
|
u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
|
|
u64 antdiv_laststatetsf;
|
|
u8 antdiv_bssid[ETH_ALEN];
|
|
};
|
|
|
|
void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
|
|
struct ath_softc *sc, int32_t rssitrig);
|
|
void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
|
|
u8 num_antcfg,
|
|
const u8 *bssid);
|
|
void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
|
|
void ath_slow_ant_div(struct ath_antdiv *antdiv,
|
|
struct ieee80211_hdr *wh,
|
|
struct ath_rx_status *rx_stats);
|
|
void ath_setdefantenna(void *sc, u32 antenna);
|
|
|
|
/*******/
|
|
/* ANI */
|
|
/*******/
|
|
|
|
/* ANI values for STA only.
|
|
FIXME: Add appropriate values for AP later */
|
|
|
|
#define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
|
|
#define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
|
|
#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
|
|
#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
|
|
|
|
struct ath_ani {
|
|
bool sc_caldone;
|
|
int16_t sc_noise_floor;
|
|
unsigned int sc_longcal_timer;
|
|
unsigned int sc_shortcal_timer;
|
|
unsigned int sc_resetcal_timer;
|
|
unsigned int sc_checkani_timer;
|
|
struct timer_list timer;
|
|
};
|
|
|
|
/********************/
|
|
/* LED Control */
|
|
/********************/
|
|
|
|
#define ATH_LED_PIN 1
|
|
|
|
enum ath_led_type {
|
|
ATH_LED_RADIO,
|
|
ATH_LED_ASSOC,
|
|
ATH_LED_TX,
|
|
ATH_LED_RX
|
|
};
|
|
|
|
struct ath_led {
|
|
struct ath_softc *sc;
|
|
struct led_classdev led_cdev;
|
|
enum ath_led_type led_type;
|
|
char name[32];
|
|
bool registered;
|
|
};
|
|
|
|
/* Rfkill */
|
|
#define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
|
|
|
|
struct ath_rfkill {
|
|
struct rfkill *rfkill;
|
|
struct delayed_work rfkill_poll;
|
|
char rfkill_name[32];
|
|
};
|
|
|
|
/********************/
|
|
/* Main driver core */
|
|
/********************/
|
|
|
|
/*
|
|
* Default cache line size, in bytes.
|
|
* Used when PCI device not fully initialized by bootrom/BIOS
|
|
*/
|
|
#define DEFAULT_CACHELINE 32
|
|
#define ATH_DEFAULT_NOISE_FLOOR -95
|
|
#define ATH_REGCLASSIDS_MAX 10
|
|
#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
|
|
#define ATH_MAX_SW_RETRIES 10
|
|
#define ATH_CHAN_MAX 255
|
|
#define IEEE80211_WEP_NKID 4 /* number of key ids */
|
|
#define IEEE80211_RATE_VAL 0x7f
|
|
/*
|
|
* The key cache is used for h/w cipher state and also for
|
|
* tracking station state such as the current tx antenna.
|
|
* We also setup a mapping table between key cache slot indices
|
|
* and station state to short-circuit node lookups on rx.
|
|
* Different parts have different size key caches. We handle
|
|
* up to ATH_KEYMAX entries (could dynamically allocate state).
|
|
*/
|
|
#define ATH_KEYMAX 128 /* max key cache size we handle */
|
|
|
|
#define ATH_IF_ID_ANY 0xff
|
|
#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
|
|
|
|
#define RSSI_LPF_THRESHOLD -20
|
|
#define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
|
|
#define ATH_RATE_DUMMY_MARKER 0
|
|
#define ATH_RSSI_LPF_LEN 10
|
|
#define ATH_RSSI_DUMMY_MARKER 0x127
|
|
|
|
#define ATH_EP_MUL(x, mul) ((x) * (mul))
|
|
#define ATH_EP_RND(x, mul) \
|
|
((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
|
|
#define ATH_RSSI_OUT(x) \
|
|
(((x) != ATH_RSSI_DUMMY_MARKER) ? \
|
|
(ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
|
|
#define ATH_RSSI_IN(x) \
|
|
(ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
|
|
#define ATH_LPF_RSSI(x, y, len) \
|
|
((x != ATH_RSSI_DUMMY_MARKER) ? \
|
|
(((x) * ((len) - 1) + (y)) / (len)) : (y))
|
|
#define ATH_RSSI_LPF(x, y) do { \
|
|
if ((y) >= RSSI_LPF_THRESHOLD) \
|
|
x = ATH_LPF_RSSI((x), \
|
|
ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
|
|
} while (0)
|
|
|
|
|
|
enum PROT_MODE {
|
|
PROT_M_NONE = 0,
|
|
PROT_M_RTSCTS,
|
|
PROT_M_CTSONLY
|
|
};
|
|
|
|
enum RATE_TYPE {
|
|
NORMAL_RATE = 0,
|
|
HALF_RATE,
|
|
QUARTER_RATE
|
|
};
|
|
|
|
struct ath_ht_info {
|
|
enum ath9k_ht_macmode tx_chan_width;
|
|
u8 ext_chan_offset;
|
|
};
|
|
|
|
#define SC_OP_INVALID BIT(0)
|
|
#define SC_OP_BEACONS BIT(1)
|
|
#define SC_OP_RXAGGR BIT(2)
|
|
#define SC_OP_TXAGGR BIT(3)
|
|
#define SC_OP_CHAINMASK_UPDATE BIT(4)
|
|
#define SC_OP_FULL_RESET BIT(5)
|
|
#define SC_OP_NO_RESET BIT(6)
|
|
#define SC_OP_PREAMBLE_SHORT BIT(7)
|
|
#define SC_OP_PROTECT_ENABLE BIT(8)
|
|
#define SC_OP_RXFLUSH BIT(9)
|
|
#define SC_OP_LED_ASSOCIATED BIT(10)
|
|
#define SC_OP_RFKILL_REGISTERED BIT(11)
|
|
#define SC_OP_RFKILL_SW_BLOCKED BIT(12)
|
|
#define SC_OP_RFKILL_HW_BLOCKED BIT(13)
|
|
|
|
struct ath_softc {
|
|
struct ieee80211_hw *hw;
|
|
struct pci_dev *pdev;
|
|
struct tasklet_struct intr_tq;
|
|
struct tasklet_struct bcon_tasklet;
|
|
struct ath_config sc_config;
|
|
struct ath_hal *sc_ah;
|
|
struct ath_rate_softc *sc_rc;
|
|
void __iomem *mem;
|
|
|
|
u8 sc_curbssid[ETH_ALEN];
|
|
u8 sc_myaddr[ETH_ALEN];
|
|
u8 sc_bssidmask[ETH_ALEN];
|
|
|
|
int sc_debug;
|
|
u32 sc_intrstatus;
|
|
u32 sc_flags; /* SC_OP_* */
|
|
unsigned int rx_filter;
|
|
u16 sc_curtxpow;
|
|
u16 sc_curaid;
|
|
u16 sc_cachelsz;
|
|
int sc_slotupdate; /* slot to next advance fsm */
|
|
int sc_slottime;
|
|
int sc_bslot[ATH_BCBUF];
|
|
u8 sc_tx_chainmask;
|
|
u8 sc_rx_chainmask;
|
|
enum ath9k_int sc_imask;
|
|
enum wireless_mode sc_curmode; /* current phy mode */
|
|
enum PROT_MODE sc_protmode;
|
|
|
|
u8 sc_nbcnvaps; /* # of vaps sending beacons */
|
|
u16 sc_nvaps; /* # of active virtual ap's */
|
|
struct ieee80211_vif *sc_vaps[ATH_BCBUF];
|
|
|
|
u8 sc_mcastantenna;
|
|
u8 sc_defant; /* current default antenna */
|
|
u8 sc_rxotherant; /* rx's on non-default antenna */
|
|
|
|
struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
|
|
struct ath_ht_info sc_ht_info;
|
|
enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
|
|
|
|
#ifdef CONFIG_SLOW_ANT_DIV
|
|
struct ath_antdiv sc_antdiv;
|
|
#endif
|
|
enum {
|
|
OK, /* no change needed */
|
|
UPDATE, /* update pending */
|
|
COMMIT /* beacon sent, commit change */
|
|
} sc_updateslot; /* slot time update fsm */
|
|
|
|
/* Crypto */
|
|
u32 sc_keymax; /* size of key cache */
|
|
DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */
|
|
u8 sc_splitmic; /* split TKIP MIC keys */
|
|
|
|
/* RX */
|
|
struct list_head sc_rxbuf;
|
|
struct ath_descdma sc_rxdma;
|
|
int sc_rxbufsize; /* rx size based on mtu */
|
|
u32 *sc_rxlink; /* link ptr in last RX desc */
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|
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/* TX */
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struct list_head sc_txbuf;
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|
struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
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|
struct ath_descdma sc_txdma;
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|
u32 sc_txqsetup;
|
|
int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
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|
u16 seq_no; /* TX sequence number */
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|
|
|
/* Beacon */
|
|
struct ath9k_tx_queue_info sc_beacon_qi;
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|
struct ath_descdma sc_bdma;
|
|
struct ath_txq *sc_cabq;
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struct list_head sc_bbuf;
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|
u32 sc_bhalq;
|
|
u32 sc_bmisscount;
|
|
u32 ast_be_xmit; /* beacons transmitted */
|
|
u64 bc_tstamp;
|
|
|
|
/* Rate */
|
|
struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
|
|
const struct ath9k_rate_table *sc_currates;
|
|
u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */
|
|
u8 sc_protrix; /* protection rate index */
|
|
struct {
|
|
u32 rateKbps; /* transfer rate in kbs */
|
|
u8 ieeerate; /* IEEE rate */
|
|
} sc_hwmap[256]; /* h/w rate ix mappings */
|
|
|
|
/* Channel, Band */
|
|
struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
|
|
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
|
|
|
|
/* Locks */
|
|
spinlock_t sc_rxflushlock;
|
|
spinlock_t sc_rxbuflock;
|
|
spinlock_t sc_txbuflock;
|
|
spinlock_t sc_resetlock;
|
|
|
|
/* LEDs */
|
|
struct ath_led radio_led;
|
|
struct ath_led assoc_led;
|
|
struct ath_led tx_led;
|
|
struct ath_led rx_led;
|
|
|
|
/* Rfkill */
|
|
struct ath_rfkill rf_kill;
|
|
|
|
/* ANI */
|
|
struct ath_ani sc_ani;
|
|
};
|
|
|
|
int ath_init(u16 devid, struct ath_softc *sc);
|
|
int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
|
|
void ath_stop(struct ath_softc *sc);
|
|
irqreturn_t ath_isr(int irq, void *dev);
|
|
int ath_reset(struct ath_softc *sc, bool retry_tx);
|
|
int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
|
|
|
|
/*********************/
|
|
/* Utility Functions */
|
|
/*********************/
|
|
|
|
void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
|
|
int ath_keyset(struct ath_softc *sc,
|
|
u16 keyix,
|
|
struct ath9k_keyval *hk,
|
|
const u8 mac[ETH_ALEN]);
|
|
int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
|
|
int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
|
|
void ath_setslottime(struct ath_softc *sc);
|
|
void ath_update_txpow(struct ath_softc *sc);
|
|
int ath_cabq_update(struct ath_softc *);
|
|
u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
|
|
|
|
#endif /* CORE_H */
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