mirror of
https://github.com/torvalds/linux.git
synced 2024-12-04 18:13:04 +00:00
384461abca
Instead of requiring each driver to care for assigning the owner member
of struct pwm_ops, handle that implicitly using a macro. Note that the
owner member has to be moved to struct pwm_chip, as the ops structure
usually lives in read-only memory and so cannot be modified.
The upside is that new low level drivers cannot forget the assignment and
save one line each. The pwm-crc driver didn't assign .owner, that's not
a problem in practice though as the driver cannot be compiled as a
module.
Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> # Intel LPSS
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> # pwm-{bcm,brcm}*.c
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> # sun4i
Acked-by: Andi Shyti <andi.shyti@kernel.org>
Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> # pwm-visconti
Acked-by: Heiko Stuebner <heiko@sntech.de> # pwm-rockchip
Acked-by: Michael Walle <michael@walle.cc> # pwm-sl28cpld
Acked-by: Neil Armstrong <neil.armstrong@linaro.org> # pwm-meson
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230804142707.412137-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
391 lines
9.8 KiB
C
391 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek Pulse Width Modulator driver
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*
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* Copyright (C) 2015 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
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*
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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/* PWM registers and bits definitions */
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#define PWMCON 0x00
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#define PWMHDUR 0x04
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#define PWMLDUR 0x08
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#define PWMGDUR 0x0c
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#define PWMWAVENUM 0x28
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#define PWMDWIDTH 0x2c
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#define PWM45DWIDTH_FIXUP 0x30
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#define PWMTHRES 0x30
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#define PWM45THRES_FIXUP 0x34
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#define PWM_CK_26M_SEL 0x210
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#define PWM_CLK_DIV_MAX 7
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struct pwm_mediatek_of_data {
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unsigned int num_pwms;
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bool pwm45_fixup;
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bool has_ck_26m_sel;
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const unsigned int *reg_offset;
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};
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/**
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* struct pwm_mediatek_chip - struct representing PWM chip
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* @chip: linux PWM chip representation
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* @regs: base address of PWM chip
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* @clk_top: the top clock generator
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* @clk_main: the clock used by PWM core
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* @clk_pwms: the clock used by each PWM channel
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* @clk_freq: the fix clock frequency of legacy MIPS SoC
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* @soc: pointer to chip's platform data
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*/
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struct pwm_mediatek_chip {
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struct pwm_chip chip;
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void __iomem *regs;
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struct clk *clk_top;
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struct clk *clk_main;
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struct clk **clk_pwms;
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const struct pwm_mediatek_of_data *soc;
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};
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static const unsigned int mtk_pwm_reg_offset_v1[] = {
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0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
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};
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static const unsigned int mtk_pwm_reg_offset_v2[] = {
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0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
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};
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static inline struct pwm_mediatek_chip *
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to_pwm_mediatek_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct pwm_mediatek_chip, chip);
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}
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static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
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struct pwm_device *pwm)
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{
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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int ret;
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ret = clk_prepare_enable(pc->clk_top);
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if (ret < 0)
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return ret;
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ret = clk_prepare_enable(pc->clk_main);
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if (ret < 0)
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goto disable_clk_top;
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ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
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if (ret < 0)
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goto disable_clk_main;
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return 0;
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disable_clk_main:
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clk_disable_unprepare(pc->clk_main);
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disable_clk_top:
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clk_disable_unprepare(pc->clk_top);
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return ret;
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}
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static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
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struct pwm_device *pwm)
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{
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
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clk_disable_unprepare(pc->clk_main);
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clk_disable_unprepare(pc->clk_top);
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}
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static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
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unsigned int num, unsigned int offset,
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u32 value)
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{
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writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
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}
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static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
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reg_thres = PWMTHRES;
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u64 resolution;
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int ret;
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ret = pwm_mediatek_clk_enable(chip, pwm);
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if (ret < 0)
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return ret;
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/* Make sure we use the bus clock and not the 26MHz clock */
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if (pc->soc->has_ck_26m_sel)
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writel(0, pc->regs + PWM_CK_26M_SEL);
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/* Using resolution in picosecond gets accuracy higher */
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resolution = (u64)NSEC_PER_SEC * 1000;
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do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
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cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
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while (cnt_period > 8191) {
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resolution *= 2;
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clkdiv++;
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cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
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resolution);
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}
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if (clkdiv > PWM_CLK_DIV_MAX) {
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pwm_mediatek_clk_disable(chip, pwm);
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dev_err(chip->dev, "period of %d ns not supported\n", period_ns);
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return -EINVAL;
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}
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if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
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/*
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* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
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* from the other PWMs on MT7623.
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*/
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reg_width = PWM45DWIDTH_FIXUP;
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reg_thres = PWM45THRES_FIXUP;
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}
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cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
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pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
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pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
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pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
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pwm_mediatek_clk_disable(chip, pwm);
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return 0;
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}
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static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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u32 value;
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int ret;
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ret = pwm_mediatek_clk_enable(chip, pwm);
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if (ret < 0)
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return ret;
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value = readl(pc->regs);
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value |= BIT(pwm->hwpwm);
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writel(value, pc->regs);
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return 0;
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}
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static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
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u32 value;
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value = readl(pc->regs);
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value &= ~BIT(pwm->hwpwm);
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writel(value, pc->regs);
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pwm_mediatek_clk_disable(chip, pwm);
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}
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static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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int err;
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if (state->polarity != PWM_POLARITY_NORMAL)
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return -EINVAL;
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if (!state->enabled) {
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if (pwm->state.enabled)
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pwm_mediatek_disable(chip, pwm);
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return 0;
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}
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err = pwm_mediatek_config(pwm->chip, pwm, state->duty_cycle, state->period);
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if (err)
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return err;
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if (!pwm->state.enabled)
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err = pwm_mediatek_enable(chip, pwm);
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return err;
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}
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static const struct pwm_ops pwm_mediatek_ops = {
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.apply = pwm_mediatek_apply,
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};
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static int pwm_mediatek_probe(struct platform_device *pdev)
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{
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struct pwm_mediatek_chip *pc;
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unsigned int i;
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int ret;
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pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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pc->soc = of_device_get_match_data(&pdev->dev);
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pc->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pc->regs))
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return PTR_ERR(pc->regs);
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pc->clk_pwms = devm_kmalloc_array(&pdev->dev, pc->soc->num_pwms,
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sizeof(*pc->clk_pwms), GFP_KERNEL);
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if (!pc->clk_pwms)
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return -ENOMEM;
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pc->clk_top = devm_clk_get(&pdev->dev, "top");
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if (IS_ERR(pc->clk_top))
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return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
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"Failed to get top clock\n");
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pc->clk_main = devm_clk_get(&pdev->dev, "main");
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if (IS_ERR(pc->clk_main))
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return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
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"Failed to get main clock\n");
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for (i = 0; i < pc->soc->num_pwms; i++) {
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char name[8];
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snprintf(name, sizeof(name), "pwm%d", i + 1);
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pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
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if (IS_ERR(pc->clk_pwms[i]))
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return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
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"Failed to get %s clock\n", name);
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}
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pc->chip.dev = &pdev->dev;
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pc->chip.ops = &pwm_mediatek_ops;
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pc->chip.npwm = pc->soc->num_pwms;
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ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
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if (ret < 0)
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return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
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return 0;
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}
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static const struct pwm_mediatek_of_data mt2712_pwm_data = {
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.num_pwms = 8,
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.pwm45_fixup = false,
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.has_ck_26m_sel = false,
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.reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt6795_pwm_data = {
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.num_pwms = 7,
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.pwm45_fixup = false,
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.has_ck_26m_sel = false,
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.reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7622_pwm_data = {
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.num_pwms = 6,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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.reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7623_pwm_data = {
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.num_pwms = 5,
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.pwm45_fixup = true,
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.has_ck_26m_sel = false,
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.reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7628_pwm_data = {
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.num_pwms = 4,
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.pwm45_fixup = true,
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.has_ck_26m_sel = false,
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.reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7629_pwm_data = {
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.num_pwms = 1,
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.pwm45_fixup = false,
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.has_ck_26m_sel = false,
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.reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7981_pwm_data = {
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.num_pwms = 3,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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.reg_offset = mtk_pwm_reg_offset_v2,
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};
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static const struct pwm_mediatek_of_data mt7986_pwm_data = {
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.num_pwms = 2,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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.reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt8183_pwm_data = {
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.num_pwms = 4,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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.reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt8365_pwm_data = {
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.num_pwms = 3,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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.reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt8516_pwm_data = {
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.num_pwms = 5,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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.reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct of_device_id pwm_mediatek_of_match[] = {
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{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
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{ .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
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{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
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{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
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{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
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{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
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{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
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{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
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{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
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{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
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{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
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{ },
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};
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MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
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static struct platform_driver pwm_mediatek_driver = {
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.driver = {
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.name = "pwm-mediatek",
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.of_match_table = pwm_mediatek_of_match,
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},
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.probe = pwm_mediatek_probe,
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};
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module_platform_driver(pwm_mediatek_driver);
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MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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MODULE_LICENSE("GPL v2");
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