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384461abca
Instead of requiring each driver to care for assigning the owner member
of struct pwm_ops, handle that implicitly using a macro. Note that the
owner member has to be moved to struct pwm_chip, as the ops structure
usually lives in read-only memory and so cannot be modified.
The upside is that new low level drivers cannot forget the assignment and
save one line each. The pwm-crc driver didn't assign .owner, that's not
a problem in practice though as the driver cannot be compiled as a
module.
Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> # Intel LPSS
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> # pwm-{bcm,brcm}*.c
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> # sun4i
Acked-by: Andi Shyti <andi.shyti@kernel.org>
Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> # pwm-visconti
Acked-by: Heiko Stuebner <heiko@sntech.de> # pwm-rockchip
Acked-by: Michael Walle <michael@walle.cc> # pwm-sl28cpld
Acked-by: Neil Armstrong <neil.armstrong@linaro.org> # pwm-meson
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230804142707.412137-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
311 lines
7.4 KiB
C
311 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 Free Electrons
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* Copyright (C) 2014 Atmel
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/mfd/atmel-hlcdc.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#define ATMEL_HLCDC_PWMCVAL_MASK GENMASK(15, 8)
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#define ATMEL_HLCDC_PWMCVAL(x) (((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK)
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#define ATMEL_HLCDC_PWMPOL BIT(4)
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#define ATMEL_HLCDC_PWMPS_MASK GENMASK(2, 0)
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#define ATMEL_HLCDC_PWMPS_MAX 0x6
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#define ATMEL_HLCDC_PWMPS(x) ((x) & ATMEL_HLCDC_PWMPS_MASK)
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struct atmel_hlcdc_pwm_errata {
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bool slow_clk_erratum;
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bool div1_clk_erratum;
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};
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struct atmel_hlcdc_pwm {
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struct pwm_chip chip;
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struct atmel_hlcdc *hlcdc;
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struct clk *cur_clk;
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const struct atmel_hlcdc_pwm_errata *errata;
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};
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static inline struct atmel_hlcdc_pwm *to_atmel_hlcdc_pwm(struct pwm_chip *chip)
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{
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return container_of(chip, struct atmel_hlcdc_pwm, chip);
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}
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static int atmel_hlcdc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct atmel_hlcdc_pwm *atmel = to_atmel_hlcdc_pwm(chip);
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struct atmel_hlcdc *hlcdc = atmel->hlcdc;
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unsigned int status;
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int ret;
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if (state->enabled) {
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struct clk *new_clk = hlcdc->slow_clk;
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u64 pwmcval = state->duty_cycle * 256;
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unsigned long clk_freq;
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u64 clk_period_ns;
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u32 pwmcfg;
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int pres;
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if (!atmel->errata || !atmel->errata->slow_clk_erratum) {
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clk_freq = clk_get_rate(new_clk);
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if (!clk_freq)
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return -EINVAL;
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clk_period_ns = (u64)NSEC_PER_SEC * 256;
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do_div(clk_period_ns, clk_freq);
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}
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/* Errata: cannot use slow clk on some IP revisions */
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if ((atmel->errata && atmel->errata->slow_clk_erratum) ||
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clk_period_ns > state->period) {
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new_clk = hlcdc->sys_clk;
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clk_freq = clk_get_rate(new_clk);
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if (!clk_freq)
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return -EINVAL;
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clk_period_ns = (u64)NSEC_PER_SEC * 256;
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do_div(clk_period_ns, clk_freq);
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}
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for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
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/* Errata: cannot divide by 1 on some IP revisions */
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if (!pres && atmel->errata &&
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atmel->errata->div1_clk_erratum)
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continue;
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if ((clk_period_ns << pres) >= state->period)
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break;
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}
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if (pres > ATMEL_HLCDC_PWMPS_MAX)
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return -EINVAL;
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pwmcfg = ATMEL_HLCDC_PWMPS(pres);
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if (new_clk != atmel->cur_clk) {
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u32 gencfg = 0;
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int ret;
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ret = clk_prepare_enable(new_clk);
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if (ret)
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return ret;
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clk_disable_unprepare(atmel->cur_clk);
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atmel->cur_clk = new_clk;
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if (new_clk == hlcdc->sys_clk)
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gencfg = ATMEL_HLCDC_CLKPWMSEL;
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ret = regmap_update_bits(hlcdc->regmap,
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ATMEL_HLCDC_CFG(0),
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ATMEL_HLCDC_CLKPWMSEL,
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gencfg);
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if (ret)
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return ret;
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}
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do_div(pwmcval, state->period);
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/*
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* The PWM duty cycle is configurable from 0/256 to 255/256 of
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* the period cycle. Hence we can't set a duty cycle occupying
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* the whole period cycle if we're asked to.
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* Set it to 255 if pwmcval is greater than 256.
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*/
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if (pwmcval > 255)
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pwmcval = 255;
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pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval);
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if (state->polarity == PWM_POLARITY_NORMAL)
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pwmcfg |= ATMEL_HLCDC_PWMPOL;
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ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
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ATMEL_HLCDC_PWMCVAL_MASK |
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ATMEL_HLCDC_PWMPS_MASK |
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ATMEL_HLCDC_PWMPOL,
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pwmcfg);
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if (ret)
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return ret;
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ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN,
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ATMEL_HLCDC_PWM);
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if (ret)
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return ret;
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ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
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status,
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status & ATMEL_HLCDC_PWM,
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10, 0);
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if (ret)
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return ret;
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} else {
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ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS,
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ATMEL_HLCDC_PWM);
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if (ret)
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return ret;
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ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
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status,
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!(status & ATMEL_HLCDC_PWM),
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10, 0);
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if (ret)
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return ret;
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clk_disable_unprepare(atmel->cur_clk);
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atmel->cur_clk = NULL;
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}
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return 0;
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}
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static const struct pwm_ops atmel_hlcdc_pwm_ops = {
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.apply = atmel_hlcdc_pwm_apply,
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};
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static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = {
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.slow_clk_erratum = true,
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};
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static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = {
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.div1_clk_erratum = true,
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};
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#ifdef CONFIG_PM_SLEEP
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static int atmel_hlcdc_pwm_suspend(struct device *dev)
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{
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struct atmel_hlcdc_pwm *atmel = dev_get_drvdata(dev);
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/* Keep the periph clock enabled if the PWM is still running. */
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if (pwm_is_enabled(&atmel->chip.pwms[0]))
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clk_disable_unprepare(atmel->hlcdc->periph_clk);
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return 0;
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}
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static int atmel_hlcdc_pwm_resume(struct device *dev)
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{
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struct atmel_hlcdc_pwm *atmel = dev_get_drvdata(dev);
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struct pwm_state state;
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int ret;
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pwm_get_state(&atmel->chip.pwms[0], &state);
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/* Re-enable the periph clock it was stopped during suspend. */
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if (!state.enabled) {
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ret = clk_prepare_enable(atmel->hlcdc->periph_clk);
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if (ret)
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return ret;
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}
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return atmel_hlcdc_pwm_apply(&atmel->chip, &atmel->chip.pwms[0],
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&state);
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}
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#endif
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static SIMPLE_DEV_PM_OPS(atmel_hlcdc_pwm_pm_ops,
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atmel_hlcdc_pwm_suspend, atmel_hlcdc_pwm_resume);
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static const struct of_device_id atmel_hlcdc_dt_ids[] = {
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{
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.compatible = "atmel,at91sam9n12-hlcdc",
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/* 9n12 has same errata as 9x5 HLCDC PWM */
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.data = &atmel_hlcdc_pwm_at91sam9x5_errata,
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},
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{
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.compatible = "atmel,at91sam9x5-hlcdc",
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.data = &atmel_hlcdc_pwm_at91sam9x5_errata,
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},
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{
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.compatible = "atmel,sama5d2-hlcdc",
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},
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{
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.compatible = "atmel,sama5d3-hlcdc",
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.data = &atmel_hlcdc_pwm_sama5d3_errata,
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},
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{
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.compatible = "atmel,sama5d4-hlcdc",
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.data = &atmel_hlcdc_pwm_sama5d3_errata,
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},
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{ .compatible = "microchip,sam9x60-hlcdc", },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids);
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static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct device *dev = &pdev->dev;
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struct atmel_hlcdc_pwm *atmel;
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struct atmel_hlcdc *hlcdc;
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int ret;
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hlcdc = dev_get_drvdata(dev->parent);
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atmel = devm_kzalloc(dev, sizeof(*atmel), GFP_KERNEL);
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if (!atmel)
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return -ENOMEM;
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ret = clk_prepare_enable(hlcdc->periph_clk);
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if (ret)
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return ret;
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match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node);
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if (match)
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atmel->errata = match->data;
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atmel->hlcdc = hlcdc;
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atmel->chip.ops = &atmel_hlcdc_pwm_ops;
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atmel->chip.dev = dev;
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atmel->chip.npwm = 1;
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ret = pwmchip_add(&atmel->chip);
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if (ret) {
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clk_disable_unprepare(hlcdc->periph_clk);
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return ret;
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}
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platform_set_drvdata(pdev, atmel);
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return 0;
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}
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static void atmel_hlcdc_pwm_remove(struct platform_device *pdev)
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{
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struct atmel_hlcdc_pwm *atmel = platform_get_drvdata(pdev);
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pwmchip_remove(&atmel->chip);
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clk_disable_unprepare(atmel->hlcdc->periph_clk);
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}
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static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = {
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{ .compatible = "atmel,hlcdc-pwm" },
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{ /* sentinel */ },
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};
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static struct platform_driver atmel_hlcdc_pwm_driver = {
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.driver = {
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.name = "atmel-hlcdc-pwm",
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.of_match_table = atmel_hlcdc_pwm_dt_ids,
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.pm = &atmel_hlcdc_pwm_pm_ops,
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},
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.probe = atmel_hlcdc_pwm_probe,
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.remove_new = atmel_hlcdc_pwm_remove,
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};
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module_platform_driver(atmel_hlcdc_pwm_driver);
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MODULE_ALIAS("platform:atmel-hlcdc-pwm");
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MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
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MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
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MODULE_LICENSE("GPL v2");
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