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730745a5c4
This is the first part of a rework of the PowerMac i2c code. It completely reworks the "low_i2c" layer. It is now more flexible, supports KeyWest, SMU and PMU i2c busses, and provides functions to match device nodes to i2c busses and adapters. This patch also extends & fix some bugs in the SMU driver related to i2c support and removes the clock spreading hacks from the pmac feature code rather than adapting them to the new API since they'll be replaced by the platform function code completely in patch 3/5 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
1048 lines
24 KiB
C
1048 lines
24 KiB
C
/*
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* arch/powerpc/platforms/powermac/low_i2c.c
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*
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* Copyright (C) 2003-2005 Ben. Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* The linux i2c layer isn't completely suitable for our needs for various
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* reasons ranging from too late initialisation to semantics not perfectly
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* matching some requirements of the apple platform functions etc...
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*
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* This file thus provides a simple low level unified i2c interface for
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* powermac that covers the various types of i2c busses used in Apple machines.
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* For now, keywest, PMU and SMU, though we could add Cuda, or other bit
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* banging busses found on older chipstes in earlier machines if we ever need
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* one of them.
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*
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* The drivers in this file are synchronous/blocking. In addition, the
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* keywest one is fairly slow due to the use of msleep instead of interrupts
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* as the interrupt is currently used by i2c-keywest. In the long run, we
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* might want to get rid of those high-level interfaces to linux i2c layer
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* either completely (converting all drivers) or replacing them all with a
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* single stub driver on top of this one. Once done, the interrupt will be
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* available for our use.
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*/
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#undef DEBUG
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#undef DEBUG_LOW
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/adb.h>
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#include <linux/pmu.h>
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#include <linux/delay.h>
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#include <linux/completion.h>
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#include <asm/keylargo.h>
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#include <asm/uninorth.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/smu.h>
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#include <asm/pmac_low_i2c.h>
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#ifdef DEBUG
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#define DBG(x...) do {\
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printk(KERN_DEBUG "low_i2c:" x); \
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} while(0)
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#else
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#define DBG(x...)
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#endif
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#ifdef DEBUG_LOW
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#define DBG_LOW(x...) do {\
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printk(KERN_DEBUG "low_i2c:" x); \
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} while(0)
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#else
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#define DBG_LOW(x...)
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#endif
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/*
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* A bus structure. Each bus in the system has such a structure associated.
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*/
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struct pmac_i2c_bus
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{
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struct list_head link;
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struct device_node *controller;
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struct device_node *busnode;
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int type;
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int flags;
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struct i2c_adapter *adapter;
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void *hostdata;
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int channel; /* some hosts have multiple */
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int mode; /* current mode */
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struct semaphore sem;
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int opened;
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int polled; /* open mode */
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/* ops */
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int (*open)(struct pmac_i2c_bus *bus);
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void (*close)(struct pmac_i2c_bus *bus);
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int (*xfer)(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
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u32 subaddr, u8 *data, int len);
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};
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static LIST_HEAD(pmac_i2c_busses);
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/*
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* Keywest implementation
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*/
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struct pmac_i2c_host_kw
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{
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struct semaphore mutex; /* Access mutex for use by
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* i2c-keywest */
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void __iomem *base; /* register base address */
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int bsteps; /* register stepping */
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int speed; /* speed */
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};
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/* Register indices */
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typedef enum {
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reg_mode = 0,
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reg_control,
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reg_status,
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reg_isr,
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reg_ier,
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reg_addr,
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reg_subaddr,
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reg_data
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} reg_t;
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/* Mode register */
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#define KW_I2C_MODE_100KHZ 0x00
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#define KW_I2C_MODE_50KHZ 0x01
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#define KW_I2C_MODE_25KHZ 0x02
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#define KW_I2C_MODE_DUMB 0x00
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#define KW_I2C_MODE_STANDARD 0x04
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#define KW_I2C_MODE_STANDARDSUB 0x08
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#define KW_I2C_MODE_COMBINED 0x0C
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#define KW_I2C_MODE_MODE_MASK 0x0C
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#define KW_I2C_MODE_CHAN_MASK 0xF0
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/* Control register */
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#define KW_I2C_CTL_AAK 0x01
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#define KW_I2C_CTL_XADDR 0x02
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#define KW_I2C_CTL_STOP 0x04
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#define KW_I2C_CTL_START 0x08
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/* Status register */
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#define KW_I2C_STAT_BUSY 0x01
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#define KW_I2C_STAT_LAST_AAK 0x02
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#define KW_I2C_STAT_LAST_RW 0x04
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#define KW_I2C_STAT_SDA 0x08
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#define KW_I2C_STAT_SCL 0x10
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/* IER & ISR registers */
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#define KW_I2C_IRQ_DATA 0x01
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#define KW_I2C_IRQ_ADDR 0x02
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#define KW_I2C_IRQ_STOP 0x04
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#define KW_I2C_IRQ_START 0x08
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#define KW_I2C_IRQ_MASK 0x0F
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/* State machine states */
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enum {
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state_idle,
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state_addr,
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state_read,
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state_write,
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state_stop,
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state_dead
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};
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#define WRONG_STATE(name) do {\
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printk(KERN_DEBUG "KW: wrong state. Got %s, state: %s (isr: %02x)\n", \
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name, __kw_state_names[state], isr); \
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} while(0)
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static const char *__kw_state_names[] = {
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"state_idle",
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"state_addr",
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"state_read",
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"state_write",
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"state_stop",
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"state_dead"
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};
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static inline u8 __kw_read_reg(struct pmac_i2c_bus *bus, reg_t reg)
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{
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struct pmac_i2c_host_kw *host = bus->hostdata;
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return readb(host->base + (((unsigned int)reg) << host->bsteps));
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}
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static inline void __kw_write_reg(struct pmac_i2c_bus *bus, reg_t reg, u8 val)
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{
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struct pmac_i2c_host_kw *host = bus->hostdata;
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writeb(val, host->base + (((unsigned)reg) << host->bsteps));
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(void)__kw_read_reg(bus, reg_subaddr);
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}
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#define kw_write_reg(reg, val) __kw_write_reg(bus, reg, val)
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#define kw_read_reg(reg) __kw_read_reg(bus, reg)
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static u8 kw_i2c_wait_interrupt(struct pmac_i2c_bus* bus)
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{
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int i, j;
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u8 isr;
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for (i = 0; i < 1000; i++) {
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isr = kw_read_reg(reg_isr) & KW_I2C_IRQ_MASK;
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if (isr != 0)
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return isr;
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/* This code is used with the timebase frozen, we cannot rely
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* on udelay nor schedule when in polled mode !
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* For now, just use a bogus loop....
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*/
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if (bus->polled) {
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for (j = 1; j < 1000000; j++)
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mb();
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} else
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msleep(1);
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}
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return isr;
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}
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static int kw_i2c_handle_interrupt(struct pmac_i2c_bus *bus, int state, int rw,
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int *rc, u8 **data, int *len, u8 isr)
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{
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u8 ack;
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DBG_LOW("kw_handle_interrupt(%s, isr: %x)\n",
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__kw_state_names[state], isr);
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if (isr == 0) {
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if (state != state_stop) {
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DBG_LOW("KW: Timeout !\n");
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*rc = -EIO;
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goto stop;
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}
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if (state == state_stop) {
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ack = kw_read_reg(reg_status);
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if (!(ack & KW_I2C_STAT_BUSY)) {
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state = state_idle;
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kw_write_reg(reg_ier, 0x00);
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}
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}
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return state;
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}
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if (isr & KW_I2C_IRQ_ADDR) {
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ack = kw_read_reg(reg_status);
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if (state != state_addr) {
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kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
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WRONG_STATE("KW_I2C_IRQ_ADDR");
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*rc = -EIO;
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goto stop;
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}
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if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
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*rc = -ENODEV;
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DBG_LOW("KW: NAK on address\n");
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return state_stop;
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} else {
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if (rw) {
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state = state_read;
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if (*len > 1)
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kw_write_reg(reg_control,
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KW_I2C_CTL_AAK);
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} else {
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state = state_write;
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kw_write_reg(reg_data, **data);
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(*data)++; (*len)--;
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}
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}
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kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
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}
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if (isr & KW_I2C_IRQ_DATA) {
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if (state == state_read) {
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**data = kw_read_reg(reg_data);
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(*data)++; (*len)--;
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kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
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if ((*len) == 0)
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state = state_stop;
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else if ((*len) == 1)
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kw_write_reg(reg_control, 0);
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} else if (state == state_write) {
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ack = kw_read_reg(reg_status);
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if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
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DBG_LOW("KW: nack on data write\n");
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*rc = -EIO;
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goto stop;
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} else if (*len) {
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kw_write_reg(reg_data, **data);
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(*data)++; (*len)--;
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} else {
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kw_write_reg(reg_control, KW_I2C_CTL_STOP);
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state = state_stop;
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*rc = 0;
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}
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kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
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} else {
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kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
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WRONG_STATE("KW_I2C_IRQ_DATA");
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if (state != state_stop) {
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*rc = -EIO;
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goto stop;
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}
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}
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}
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if (isr & KW_I2C_IRQ_STOP) {
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kw_write_reg(reg_isr, KW_I2C_IRQ_STOP);
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if (state != state_stop) {
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WRONG_STATE("KW_I2C_IRQ_STOP");
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*rc = -EIO;
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}
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return state_idle;
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}
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if (isr & KW_I2C_IRQ_START)
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kw_write_reg(reg_isr, KW_I2C_IRQ_START);
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return state;
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stop:
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kw_write_reg(reg_control, KW_I2C_CTL_STOP);
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return state_stop;
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}
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static int kw_i2c_open(struct pmac_i2c_bus *bus)
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{
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struct pmac_i2c_host_kw *host = bus->hostdata;
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down(&host->mutex);
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return 0;
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}
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static void kw_i2c_close(struct pmac_i2c_bus *bus)
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{
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struct pmac_i2c_host_kw *host = bus->hostdata;
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up(&host->mutex);
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}
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static int kw_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
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u32 subaddr, u8 *data, int len)
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{
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struct pmac_i2c_host_kw *host = bus->hostdata;
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u8 mode_reg = host->speed;
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int state = state_addr;
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int rc = 0;
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/* Setup mode & subaddress if any */
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switch(bus->mode) {
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case pmac_i2c_mode_dumb:
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return -EINVAL;
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case pmac_i2c_mode_std:
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mode_reg |= KW_I2C_MODE_STANDARD;
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if (subsize != 0)
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return -EINVAL;
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break;
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case pmac_i2c_mode_stdsub:
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mode_reg |= KW_I2C_MODE_STANDARDSUB;
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if (subsize != 1)
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return -EINVAL;
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break;
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case pmac_i2c_mode_combined:
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mode_reg |= KW_I2C_MODE_COMBINED;
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if (subsize != 1)
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return -EINVAL;
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break;
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}
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/* Setup channel & clear pending irqs */
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kw_write_reg(reg_isr, kw_read_reg(reg_isr));
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kw_write_reg(reg_mode, mode_reg | (bus->channel << 4));
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kw_write_reg(reg_status, 0);
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/* Set up address and r/w bit, strip possible stale bus number from
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* address top bits
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*/
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kw_write_reg(reg_addr, addrdir & 0xff);
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/* Set up the sub address */
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if ((mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB
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|| (mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_COMBINED)
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kw_write_reg(reg_subaddr, subaddr);
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/* Start sending address & disable interrupt*/
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kw_write_reg(reg_ier, 0 /*KW_I2C_IRQ_MASK*/);
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kw_write_reg(reg_control, KW_I2C_CTL_XADDR);
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/* State machine, to turn into an interrupt handler in the future */
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while(state != state_idle) {
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u8 isr = kw_i2c_wait_interrupt(bus);
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state = kw_i2c_handle_interrupt(bus, state, addrdir & 1, &rc,
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&data, &len, isr);
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}
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return rc;
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}
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static struct pmac_i2c_host_kw *__init kw_i2c_host_init(struct device_node *np)
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{
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struct pmac_i2c_host_kw *host;
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u32 *psteps, *prate, *addrp, steps;
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host = kzalloc(sizeof(struct pmac_i2c_host_kw), GFP_KERNEL);
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if (host == NULL) {
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printk(KERN_ERR "low_i2c: Can't allocate host for %s\n",
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np->full_name);
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return NULL;
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}
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/* Apple is kind enough to provide a valid AAPL,address property
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* on all i2c keywest nodes so far ... we would have to fallback
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* to macio parsing if that wasn't the case
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*/
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addrp = (u32 *)get_property(np, "AAPL,address", NULL);
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if (addrp == NULL) {
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printk(KERN_ERR "low_i2c: Can't find address for %s\n",
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np->full_name);
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kfree(host);
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return NULL;
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}
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init_MUTEX(&host->mutex);
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psteps = (u32 *)get_property(np, "AAPL,address-step", NULL);
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steps = psteps ? (*psteps) : 0x10;
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for (host->bsteps = 0; (steps & 0x01) == 0; host->bsteps++)
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steps >>= 1;
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/* Select interface rate */
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host->speed = KW_I2C_MODE_25KHZ;
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prate = (u32 *)get_property(np, "AAPL,i2c-rate", NULL);
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if (prate) switch(*prate) {
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case 100:
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host->speed = KW_I2C_MODE_100KHZ;
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break;
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case 50:
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host->speed = KW_I2C_MODE_50KHZ;
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break;
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case 25:
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host->speed = KW_I2C_MODE_25KHZ;
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break;
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}
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printk(KERN_INFO "KeyWest i2c @0x%08x %s\n", *addrp, np->full_name);
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host->base = ioremap((*addrp), 0x1000);
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return host;
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}
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static void __init kw_i2c_add(struct pmac_i2c_host_kw *host,
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struct device_node *controller,
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struct device_node *busnode,
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int channel)
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{
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struct pmac_i2c_bus *bus;
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bus = kzalloc(sizeof(struct pmac_i2c_bus), GFP_KERNEL);
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if (bus == NULL)
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return;
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bus->controller = of_node_get(controller);
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bus->busnode = of_node_get(busnode);
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bus->type = pmac_i2c_bus_keywest;
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bus->hostdata = host;
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bus->channel = channel;
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bus->mode = pmac_i2c_mode_std;
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bus->open = kw_i2c_open;
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bus->close = kw_i2c_close;
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bus->xfer = kw_i2c_xfer;
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init_MUTEX(&bus->sem);
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if (controller == busnode)
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bus->flags = pmac_i2c_multibus;
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list_add(&bus->link, &pmac_i2c_busses);
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printk(KERN_INFO " channel %d bus %s\n", channel,
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(controller == busnode) ? "<multibus>" : busnode->full_name);
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}
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static void __init kw_i2c_probe(void)
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{
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struct device_node *np, *child, *parent;
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/* Probe keywest-i2c busses */
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for (np = NULL;
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(np = of_find_compatible_node(np, "i2c","keywest-i2c")) != NULL;){
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struct pmac_i2c_host_kw *host;
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int multibus, chans, i;
|
|
|
|
/* Found one, init a host structure */
|
|
host = kw_i2c_host_init(np);
|
|
if (host == NULL)
|
|
continue;
|
|
|
|
/* Now check if we have a multibus setup (old style) or if we
|
|
* have proper bus nodes. Note that the "new" way (proper bus
|
|
* nodes) might cause us to not create some busses that are
|
|
* kept hidden in the device-tree. In the future, we might
|
|
* want to work around that by creating busses without a node
|
|
* but not for now
|
|
*/
|
|
child = of_get_next_child(np, NULL);
|
|
multibus = !child || strcmp(child->name, "i2c-bus");
|
|
of_node_put(child);
|
|
|
|
/* For a multibus setup, we get the bus count based on the
|
|
* parent type
|
|
*/
|
|
if (multibus) {
|
|
parent = of_get_parent(np);
|
|
if (parent == NULL)
|
|
continue;
|
|
chans = parent->name[0] == 'u' ? 2 : 1;
|
|
for (i = 0; i < chans; i++)
|
|
kw_i2c_add(host, np, np, i);
|
|
} else {
|
|
for (child = NULL;
|
|
(child = of_get_next_child(np, child)) != NULL;) {
|
|
u32 *reg =
|
|
(u32 *)get_property(child, "reg", NULL);
|
|
if (reg == NULL)
|
|
continue;
|
|
kw_i2c_add(host, np, child, *reg);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
*
|
|
* PMU implementation
|
|
*
|
|
*/
|
|
|
|
#ifdef CONFIG_ADB_PMU
|
|
|
|
/*
|
|
* i2c command block to the PMU
|
|
*/
|
|
struct pmu_i2c_hdr {
|
|
u8 bus;
|
|
u8 mode;
|
|
u8 bus2;
|
|
u8 address;
|
|
u8 sub_addr;
|
|
u8 comb_addr;
|
|
u8 count;
|
|
u8 data[];
|
|
};
|
|
|
|
static void pmu_i2c_complete(struct adb_request *req)
|
|
{
|
|
complete(req->arg);
|
|
}
|
|
|
|
static int pmu_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
|
|
u32 subaddr, u8 *data, int len)
|
|
{
|
|
struct adb_request *req = bus->hostdata;
|
|
struct pmu_i2c_hdr *hdr = (struct pmu_i2c_hdr *)&req->data[1];
|
|
struct completion comp;
|
|
int read = addrdir & 1;
|
|
int retry;
|
|
int rc = 0;
|
|
|
|
/* For now, limit ourselves to 16 bytes transfers */
|
|
if (len > 16)
|
|
return -EINVAL;
|
|
|
|
init_completion(&comp);
|
|
|
|
for (retry = 0; retry < 16; retry++) {
|
|
memset(req, 0, sizeof(struct adb_request));
|
|
hdr->bus = bus->channel;
|
|
hdr->count = len;
|
|
|
|
switch(bus->mode) {
|
|
case pmac_i2c_mode_std:
|
|
if (subsize != 0)
|
|
return -EINVAL;
|
|
hdr->address = addrdir;
|
|
hdr->mode = PMU_I2C_MODE_SIMPLE;
|
|
break;
|
|
case pmac_i2c_mode_stdsub:
|
|
case pmac_i2c_mode_combined:
|
|
if (subsize != 1)
|
|
return -EINVAL;
|
|
hdr->address = addrdir & 0xfe;
|
|
hdr->comb_addr = addrdir;
|
|
hdr->sub_addr = subaddr;
|
|
if (bus->mode == pmac_i2c_mode_stdsub)
|
|
hdr->mode = PMU_I2C_MODE_STDSUB;
|
|
else
|
|
hdr->mode = PMU_I2C_MODE_COMBINED;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
INIT_COMPLETION(comp);
|
|
req->data[0] = PMU_I2C_CMD;
|
|
req->reply[0] = 0xff;
|
|
req->nbytes = sizeof(struct pmu_i2c_hdr) + 1;
|
|
req->done = pmu_i2c_complete;
|
|
req->arg = ∁
|
|
if (!read) {
|
|
memcpy(hdr->data, data, len);
|
|
req->nbytes += len;
|
|
}
|
|
rc = pmu_queue_request(req);
|
|
if (rc)
|
|
return rc;
|
|
wait_for_completion(&comp);
|
|
if (req->reply[0] == PMU_I2C_STATUS_OK)
|
|
break;
|
|
msleep(15);
|
|
}
|
|
if (req->reply[0] != PMU_I2C_STATUS_OK)
|
|
return -EIO;
|
|
|
|
for (retry = 0; retry < 16; retry++) {
|
|
memset(req, 0, sizeof(struct adb_request));
|
|
|
|
/* I know that looks like a lot, slow as hell, but darwin
|
|
* does it so let's be on the safe side for now
|
|
*/
|
|
msleep(15);
|
|
|
|
hdr->bus = PMU_I2C_BUS_STATUS;
|
|
|
|
INIT_COMPLETION(comp);
|
|
req->data[0] = PMU_I2C_CMD;
|
|
req->reply[0] = 0xff;
|
|
req->nbytes = 2;
|
|
req->done = pmu_i2c_complete;
|
|
req->arg = ∁
|
|
rc = pmu_queue_request(req);
|
|
if (rc)
|
|
return rc;
|
|
wait_for_completion(&comp);
|
|
|
|
if (req->reply[0] == PMU_I2C_STATUS_OK && !read)
|
|
return 0;
|
|
if (req->reply[0] == PMU_I2C_STATUS_DATAREAD && read) {
|
|
int rlen = req->reply_len - 1;
|
|
|
|
if (rlen != len) {
|
|
printk(KERN_WARNING "low_i2c: PMU returned %d"
|
|
" bytes, expected %d !\n", rlen, len);
|
|
return -EIO;
|
|
}
|
|
memcpy(data, &req->reply[1], len);
|
|
return 0;
|
|
}
|
|
}
|
|
return -EIO;
|
|
}
|
|
|
|
static void __init pmu_i2c_probe(void)
|
|
{
|
|
struct pmac_i2c_bus *bus;
|
|
struct device_node *busnode;
|
|
int channel, sz;
|
|
|
|
if (!pmu_present())
|
|
return;
|
|
|
|
/* There might or might not be a "pmu-i2c" node, we use that
|
|
* or via-pmu itself, whatever we find. I haven't seen a machine
|
|
* with separate bus nodes, so we assume a multibus setup
|
|
*/
|
|
busnode = of_find_node_by_name(NULL, "pmu-i2c");
|
|
if (busnode == NULL)
|
|
busnode = of_find_node_by_name(NULL, "via-pmu");
|
|
if (busnode == NULL)
|
|
return;
|
|
|
|
printk(KERN_INFO "PMU i2c %s\n", busnode->full_name);
|
|
|
|
/*
|
|
* We add bus 1 and 2 only for now, bus 0 is "special"
|
|
*/
|
|
for (channel = 1; channel <= 2; channel++) {
|
|
sz = sizeof(struct pmac_i2c_bus) + sizeof(struct adb_request);
|
|
bus = kzalloc(sz, GFP_KERNEL);
|
|
if (bus == NULL)
|
|
return;
|
|
|
|
bus->controller = busnode;
|
|
bus->busnode = busnode;
|
|
bus->type = pmac_i2c_bus_pmu;
|
|
bus->channel = channel;
|
|
bus->mode = pmac_i2c_mode_std;
|
|
bus->hostdata = bus + 1;
|
|
bus->xfer = pmu_i2c_xfer;
|
|
init_MUTEX(&bus->sem);
|
|
bus->flags = pmac_i2c_multibus;
|
|
list_add(&bus->link, &pmac_i2c_busses);
|
|
|
|
printk(KERN_INFO " channel %d bus <multibus>\n", channel);
|
|
}
|
|
}
|
|
|
|
#endif /* CONFIG_ADB_PMU */
|
|
|
|
|
|
/*
|
|
*
|
|
* SMU implementation
|
|
*
|
|
*/
|
|
|
|
#ifdef CONFIG_PMAC_SMU
|
|
|
|
static void smu_i2c_complete(struct smu_i2c_cmd *cmd, void *misc)
|
|
{
|
|
complete(misc);
|
|
}
|
|
|
|
static int smu_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
|
|
u32 subaddr, u8 *data, int len)
|
|
{
|
|
struct smu_i2c_cmd *cmd = bus->hostdata;
|
|
struct completion comp;
|
|
int read = addrdir & 1;
|
|
int rc = 0;
|
|
|
|
memset(cmd, 0, sizeof(struct smu_i2c_cmd));
|
|
cmd->info.bus = bus->channel;
|
|
cmd->info.devaddr = addrdir;
|
|
cmd->info.datalen = len;
|
|
|
|
switch(bus->mode) {
|
|
case pmac_i2c_mode_std:
|
|
if (subsize != 0)
|
|
return -EINVAL;
|
|
cmd->info.type = SMU_I2C_TRANSFER_SIMPLE;
|
|
break;
|
|
case pmac_i2c_mode_stdsub:
|
|
case pmac_i2c_mode_combined:
|
|
if (subsize > 3 || subsize < 1)
|
|
return -EINVAL;
|
|
cmd->info.sublen = subsize;
|
|
/* that's big-endian only but heh ! */
|
|
memcpy(&cmd->info.subaddr, ((char *)&subaddr) + (4 - subsize),
|
|
subsize);
|
|
if (bus->mode == pmac_i2c_mode_stdsub)
|
|
cmd->info.type = SMU_I2C_TRANSFER_STDSUB;
|
|
else
|
|
cmd->info.type = SMU_I2C_TRANSFER_COMBINED;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
if (!read)
|
|
memcpy(cmd->info.data, data, len);
|
|
|
|
init_completion(&comp);
|
|
cmd->done = smu_i2c_complete;
|
|
cmd->misc = ∁
|
|
rc = smu_queue_i2c(cmd);
|
|
if (rc < 0)
|
|
return rc;
|
|
wait_for_completion(&comp);
|
|
rc = cmd->status;
|
|
|
|
if (read)
|
|
memcpy(data, cmd->info.data, len);
|
|
return rc < 0 ? rc : 0;
|
|
}
|
|
|
|
static void __init smu_i2c_probe(void)
|
|
{
|
|
struct device_node *controller, *busnode;
|
|
struct pmac_i2c_bus *bus;
|
|
u32 *reg;
|
|
int sz;
|
|
|
|
if (!smu_present())
|
|
return;
|
|
|
|
controller = of_find_node_by_name(NULL, "smu_i2c_control");
|
|
if (controller == NULL)
|
|
controller = of_find_node_by_name(NULL, "smu");
|
|
if (controller == NULL)
|
|
return;
|
|
|
|
printk(KERN_INFO "SMU i2c %s\n", controller->full_name);
|
|
|
|
/* Look for childs, note that they might not be of the right
|
|
* type as older device trees mix i2c busses and other thigns
|
|
* at the same level
|
|
*/
|
|
for (busnode = NULL;
|
|
(busnode = of_get_next_child(controller, busnode)) != NULL;) {
|
|
if (strcmp(busnode->type, "i2c") &&
|
|
strcmp(busnode->type, "i2c-bus"))
|
|
continue;
|
|
reg = (u32 *)get_property(busnode, "reg", NULL);
|
|
if (reg == NULL)
|
|
continue;
|
|
|
|
sz = sizeof(struct pmac_i2c_bus) + sizeof(struct smu_i2c_cmd);
|
|
bus = kzalloc(sz, GFP_KERNEL);
|
|
if (bus == NULL)
|
|
return;
|
|
|
|
bus->controller = controller;
|
|
bus->busnode = of_node_get(busnode);
|
|
bus->type = pmac_i2c_bus_smu;
|
|
bus->channel = *reg;
|
|
bus->mode = pmac_i2c_mode_std;
|
|
bus->hostdata = bus + 1;
|
|
bus->xfer = smu_i2c_xfer;
|
|
init_MUTEX(&bus->sem);
|
|
bus->flags = 0;
|
|
list_add(&bus->link, &pmac_i2c_busses);
|
|
|
|
printk(KERN_INFO " channel %x bus %s\n",
|
|
bus->channel, busnode->full_name);
|
|
}
|
|
}
|
|
|
|
#endif /* CONFIG_PMAC_SMU */
|
|
|
|
/*
|
|
*
|
|
* Core code
|
|
*
|
|
*/
|
|
|
|
|
|
struct pmac_i2c_bus *pmac_i2c_find_bus(struct device_node *node)
|
|
{
|
|
struct device_node *p = of_node_get(node);
|
|
struct device_node *prev = NULL;
|
|
struct pmac_i2c_bus *bus;
|
|
|
|
while(p) {
|
|
list_for_each_entry(bus, &pmac_i2c_busses, link) {
|
|
if (p == bus->busnode) {
|
|
if (prev && bus->flags & pmac_i2c_multibus) {
|
|
u32 *reg;
|
|
reg = (u32 *)get_property(prev, "reg",
|
|
NULL);
|
|
if (!reg)
|
|
continue;
|
|
if (((*reg) >> 8) != bus->channel)
|
|
continue;
|
|
}
|
|
of_node_put(p);
|
|
of_node_put(prev);
|
|
return bus;
|
|
}
|
|
}
|
|
of_node_put(prev);
|
|
prev = p;
|
|
p = of_get_parent(p);
|
|
}
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_find_bus);
|
|
|
|
u8 pmac_i2c_get_dev_addr(struct device_node *device)
|
|
{
|
|
u32 *reg = (u32 *)get_property(device, "reg", NULL);
|
|
|
|
if (reg == NULL)
|
|
return 0;
|
|
|
|
return (*reg) & 0xff;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_get_dev_addr);
|
|
|
|
struct device_node *pmac_i2c_get_controller(struct pmac_i2c_bus *bus)
|
|
{
|
|
return bus->controller;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_get_controller);
|
|
|
|
struct device_node *pmac_i2c_get_bus_node(struct pmac_i2c_bus *bus)
|
|
{
|
|
return bus->busnode;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_get_bus_node);
|
|
|
|
int pmac_i2c_get_type(struct pmac_i2c_bus *bus)
|
|
{
|
|
return bus->type;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_get_type);
|
|
|
|
int pmac_i2c_get_flags(struct pmac_i2c_bus *bus)
|
|
{
|
|
return bus->flags;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_get_flags);
|
|
|
|
void pmac_i2c_attach_adapter(struct pmac_i2c_bus *bus,
|
|
struct i2c_adapter *adapter)
|
|
{
|
|
WARN_ON(bus->adapter != NULL);
|
|
bus->adapter = adapter;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_attach_adapter);
|
|
|
|
void pmac_i2c_detach_adapter(struct pmac_i2c_bus *bus,
|
|
struct i2c_adapter *adapter)
|
|
{
|
|
WARN_ON(bus->adapter != adapter);
|
|
bus->adapter = NULL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_detach_adapter);
|
|
|
|
struct i2c_adapter *pmac_i2c_get_adapter(struct pmac_i2c_bus *bus)
|
|
{
|
|
return bus->adapter;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_get_adapter);
|
|
|
|
extern int pmac_i2c_match_adapter(struct device_node *dev,
|
|
struct i2c_adapter *adapter)
|
|
{
|
|
struct pmac_i2c_bus *bus = pmac_i2c_find_bus(dev);
|
|
|
|
if (bus == NULL)
|
|
return 0;
|
|
return (bus->adapter == adapter);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_match_adapter);
|
|
|
|
int pmac_low_i2c_lock(struct device_node *np)
|
|
{
|
|
struct pmac_i2c_bus *bus, *found = NULL;
|
|
|
|
list_for_each_entry(bus, &pmac_i2c_busses, link) {
|
|
if (np == bus->controller) {
|
|
found = bus;
|
|
break;
|
|
}
|
|
}
|
|
if (!found)
|
|
return -ENODEV;
|
|
return pmac_i2c_open(bus, 0);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_low_i2c_lock);
|
|
|
|
int pmac_low_i2c_unlock(struct device_node *np)
|
|
{
|
|
struct pmac_i2c_bus *bus, *found = NULL;
|
|
|
|
list_for_each_entry(bus, &pmac_i2c_busses, link) {
|
|
if (np == bus->controller) {
|
|
found = bus;
|
|
break;
|
|
}
|
|
}
|
|
if (!found)
|
|
return -ENODEV;
|
|
pmac_i2c_close(bus);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_low_i2c_unlock);
|
|
|
|
|
|
int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled)
|
|
{
|
|
int rc;
|
|
|
|
down(&bus->sem);
|
|
bus->polled = polled;
|
|
bus->opened = 1;
|
|
bus->mode = pmac_i2c_mode_std;
|
|
if (bus->open && (rc = bus->open(bus)) != 0) {
|
|
bus->opened = 0;
|
|
up(&bus->sem);
|
|
return rc;
|
|
}
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_open);
|
|
|
|
void pmac_i2c_close(struct pmac_i2c_bus *bus)
|
|
{
|
|
WARN_ON(!bus->opened);
|
|
if (bus->close)
|
|
bus->close(bus);
|
|
bus->opened = 0;
|
|
up(&bus->sem);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_close);
|
|
|
|
int pmac_i2c_setmode(struct pmac_i2c_bus *bus, int mode)
|
|
{
|
|
WARN_ON(!bus->opened);
|
|
|
|
/* Report me if you see the error below as there might be a new
|
|
* "combined4" mode that I need to implement for the SMU bus
|
|
*/
|
|
if (mode < pmac_i2c_mode_dumb || mode > pmac_i2c_mode_combined) {
|
|
printk(KERN_ERR "low_i2c: Invalid mode %d requested on"
|
|
" bus %s !\n", mode, bus->busnode->full_name);
|
|
return -EINVAL;
|
|
}
|
|
bus->mode = mode;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_setmode);
|
|
|
|
int pmac_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
|
|
u32 subaddr, u8 *data, int len)
|
|
{
|
|
int rc;
|
|
|
|
WARN_ON(!bus->opened);
|
|
|
|
DBG("xfer() chan=%d, addrdir=0x%x, mode=%d, subsize=%d, subaddr=0x%x,"
|
|
" %d bytes, bus %s\n", bus->channel, addrdir, bus->mode, subsize,
|
|
subaddr, len, bus->busnode->full_name);
|
|
|
|
rc = bus->xfer(bus, addrdir, subsize, subaddr, data, len);
|
|
|
|
#ifdef DEBUG
|
|
if (rc)
|
|
DBG("xfer error %d\n", rc);
|
|
#endif
|
|
return rc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pmac_i2c_xfer);
|
|
|
|
/*
|
|
* Initialize us: probe all i2c busses on the machine and instantiate
|
|
* busses.
|
|
*/
|
|
/* This is non-static as it might be called early by smp code */
|
|
int __init pmac_i2c_init(void)
|
|
{
|
|
static int i2c_inited;
|
|
|
|
if (i2c_inited)
|
|
return 0;
|
|
i2c_inited = 1;
|
|
|
|
/* Probe keywest-i2c busses */
|
|
kw_i2c_probe();
|
|
|
|
#ifdef CONFIG_ADB_PMU
|
|
pmu_i2c_probe();
|
|
#endif
|
|
|
|
#ifdef CONFIG_PMAC_SMU
|
|
smu_i2c_probe();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
arch_initcall(pmac_i2c_init);
|
|
|