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e402acdb66
Sometimes it is required to know when the controller reset has completed and also if it has completed successfully. For such places, we call hisi_sas_controller_reset() directly before. That may lead to multiple calls to this function. This patch create a per-reset structure which contains a completion structure and status flag to know when the reset completes and also the status. It is also in hisi_hba.wq to do reset work. As all host reset works are done in hisi_hba.wq, we don't worry multiple calls to hisi_sas_controller_reset(). Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
457 lines
12 KiB
C
457 lines
12 KiB
C
/*
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* Copyright (c) 2015 Linaro Ltd.
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* Copyright (c) 2015 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef _HISI_SAS_H_
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#define _HISI_SAS_H_
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/dmapool.h>
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <scsi/sas_ata.h>
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#include <scsi/libsas.h>
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#define HISI_SAS_MAX_PHYS 9
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#define HISI_SAS_MAX_QUEUES 32
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#define HISI_SAS_QUEUE_SLOTS 512
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#define HISI_SAS_MAX_ITCT_ENTRIES 1024
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#define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES
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#define HISI_SAS_RESET_BIT 0
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#define HISI_SAS_REJECT_CMD_BIT 1
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#define HISI_SAS_STATUS_BUF_SZ (sizeof(struct hisi_sas_status_buffer))
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#define HISI_SAS_COMMAND_TABLE_SZ (sizeof(union hisi_sas_command_table))
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#define hisi_sas_status_buf_addr(buf) \
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(buf + offsetof(struct hisi_sas_slot_buf_table, status_buffer))
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#define hisi_sas_status_buf_addr_mem(slot) hisi_sas_status_buf_addr(slot->buf)
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#define hisi_sas_status_buf_addr_dma(slot) \
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hisi_sas_status_buf_addr(slot->buf_dma)
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#define hisi_sas_cmd_hdr_addr(buf) \
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(buf + offsetof(struct hisi_sas_slot_buf_table, command_header))
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#define hisi_sas_cmd_hdr_addr_mem(slot) hisi_sas_cmd_hdr_addr(slot->buf)
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#define hisi_sas_cmd_hdr_addr_dma(slot) hisi_sas_cmd_hdr_addr(slot->buf_dma)
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#define hisi_sas_sge_addr(buf) \
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(buf + offsetof(struct hisi_sas_slot_buf_table, sge_page))
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#define hisi_sas_sge_addr_mem(slot) hisi_sas_sge_addr(slot->buf)
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#define hisi_sas_sge_addr_dma(slot) hisi_sas_sge_addr(slot->buf_dma)
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#define HISI_SAS_MAX_SSP_RESP_SZ (sizeof(struct ssp_frame_hdr) + 1024)
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#define HISI_SAS_MAX_SMP_RESP_SZ 1028
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#define HISI_SAS_MAX_STP_RESP_SZ 28
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#define DEV_IS_EXPANDER(type) \
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((type == SAS_EDGE_EXPANDER_DEVICE) || \
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(type == SAS_FANOUT_EXPANDER_DEVICE))
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#define HISI_SAS_SATA_PROTOCOL_NONDATA 0x1
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#define HISI_SAS_SATA_PROTOCOL_PIO 0x2
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#define HISI_SAS_SATA_PROTOCOL_DMA 0x4
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#define HISI_SAS_SATA_PROTOCOL_FPDMA 0x8
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#define HISI_SAS_SATA_PROTOCOL_ATAPI 0x10
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struct hisi_hba;
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enum {
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PORT_TYPE_SAS = (1U << 1),
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PORT_TYPE_SATA = (1U << 0),
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};
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enum dev_status {
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HISI_SAS_DEV_NORMAL,
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HISI_SAS_DEV_EH,
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};
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enum {
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HISI_SAS_INT_ABT_CMD = 0,
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HISI_SAS_INT_ABT_DEV = 1,
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};
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enum hisi_sas_dev_type {
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HISI_SAS_DEV_TYPE_STP = 0,
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HISI_SAS_DEV_TYPE_SSP,
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HISI_SAS_DEV_TYPE_SATA,
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};
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struct hisi_sas_hw_error {
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u32 irq_msk;
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u32 msk;
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int shift;
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const char *msg;
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int reg;
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const struct hisi_sas_hw_error *sub;
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};
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struct hisi_sas_rst {
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struct hisi_hba *hisi_hba;
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struct completion *completion;
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struct work_struct work;
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bool done;
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};
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#define HISI_SAS_RST_WORK_INIT(r, c) \
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{ .hisi_hba = hisi_hba, \
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.completion = &c, \
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.work = __WORK_INITIALIZER(r.work, \
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hisi_sas_sync_rst_work_handler), \
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.done = false, \
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}
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#define HISI_SAS_DECLARE_RST_WORK_ON_STACK(r) \
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DECLARE_COMPLETION_ONSTACK(c); \
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DECLARE_WORK(w, hisi_sas_sync_rst_work_handler); \
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struct hisi_sas_rst r = HISI_SAS_RST_WORK_INIT(r, c)
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enum hisi_sas_bit_err_type {
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HISI_SAS_ERR_SINGLE_BIT_ECC = 0x0,
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HISI_SAS_ERR_MULTI_BIT_ECC = 0x1,
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};
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struct hisi_sas_phy {
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struct hisi_hba *hisi_hba;
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struct hisi_sas_port *port;
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struct asd_sas_phy sas_phy;
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struct sas_identify identify;
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struct work_struct phyup_ws;
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u64 port_id; /* from hw */
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u64 dev_sas_addr;
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u64 frame_rcvd_size;
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u8 frame_rcvd[32];
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u8 phy_attached;
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u8 reserved[3];
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u32 phy_type;
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enum sas_linkrate minimum_linkrate;
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enum sas_linkrate maximum_linkrate;
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};
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struct hisi_sas_port {
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struct asd_sas_port sas_port;
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u8 port_attached;
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u8 id; /* from hw */
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};
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struct hisi_sas_cq {
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struct hisi_hba *hisi_hba;
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struct tasklet_struct tasklet;
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int rd_point;
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int id;
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};
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struct hisi_sas_dq {
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struct hisi_hba *hisi_hba;
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struct hisi_sas_slot *slot_prep;
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spinlock_t lock;
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int wr_point;
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int id;
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};
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struct hisi_sas_device {
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struct hisi_hba *hisi_hba;
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struct domain_device *sas_device;
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struct completion *completion;
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struct hisi_sas_dq *dq;
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struct list_head list;
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u64 attached_phy;
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atomic64_t running_req;
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enum sas_device_type dev_type;
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int device_id;
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int sata_idx;
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u8 dev_status;
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};
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struct hisi_sas_slot {
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struct list_head entry;
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struct sas_task *task;
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struct hisi_sas_port *port;
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u64 n_elem;
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int dlvry_queue;
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int dlvry_queue_slot;
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int cmplt_queue;
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int cmplt_queue_slot;
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int idx;
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int abort;
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void *buf;
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dma_addr_t buf_dma;
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void *cmd_hdr;
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dma_addr_t cmd_hdr_dma;
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struct work_struct abort_slot;
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struct timer_list internal_abort_timer;
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};
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struct hisi_sas_tmf_task {
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u8 tmf;
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u16 tag_of_task_to_be_managed;
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};
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struct hisi_sas_hw {
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int (*hw_init)(struct hisi_hba *hisi_hba);
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void (*setup_itct)(struct hisi_hba *hisi_hba,
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struct hisi_sas_device *device);
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int (*slot_index_alloc)(struct hisi_hba *hisi_hba, int *slot_idx,
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struct domain_device *device);
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struct hisi_sas_device *(*alloc_dev)(struct domain_device *device);
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void (*sl_notify)(struct hisi_hba *hisi_hba, int phy_no);
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int (*get_free_slot)(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq);
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void (*start_delivery)(struct hisi_sas_dq *dq);
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int (*prep_ssp)(struct hisi_hba *hisi_hba,
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struct hisi_sas_slot *slot, int is_tmf,
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struct hisi_sas_tmf_task *tmf);
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int (*prep_smp)(struct hisi_hba *hisi_hba,
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struct hisi_sas_slot *slot);
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int (*prep_stp)(struct hisi_hba *hisi_hba,
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struct hisi_sas_slot *slot);
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int (*prep_abort)(struct hisi_hba *hisi_hba,
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struct hisi_sas_slot *slot,
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int device_id, int abort_flag, int tag_to_abort);
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int (*slot_complete)(struct hisi_hba *hisi_hba,
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struct hisi_sas_slot *slot);
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void (*phys_init)(struct hisi_hba *hisi_hba);
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void (*phy_start)(struct hisi_hba *hisi_hba, int phy_no);
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void (*phy_disable)(struct hisi_hba *hisi_hba, int phy_no);
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void (*phy_hard_reset)(struct hisi_hba *hisi_hba, int phy_no);
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void (*get_events)(struct hisi_hba *hisi_hba, int phy_no);
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void (*phy_set_linkrate)(struct hisi_hba *hisi_hba, int phy_no,
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struct sas_phy_linkrates *linkrates);
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enum sas_linkrate (*phy_get_max_linkrate)(void);
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void (*clear_itct)(struct hisi_hba *hisi_hba,
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struct hisi_sas_device *dev);
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void (*free_device)(struct hisi_sas_device *sas_dev);
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int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id);
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void (*dereg_device)(struct hisi_hba *hisi_hba,
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struct domain_device *device);
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int (*soft_reset)(struct hisi_hba *hisi_hba);
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u32 (*get_phys_state)(struct hisi_hba *hisi_hba);
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int max_command_entries;
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int complete_hdr_size;
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};
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struct hisi_hba {
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/* This must be the first element, used by SHOST_TO_SAS_HA */
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struct sas_ha_struct *p;
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struct platform_device *platform_dev;
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struct pci_dev *pci_dev;
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struct device *dev;
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void __iomem *regs;
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struct regmap *ctrl;
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u32 ctrl_reset_reg;
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u32 ctrl_reset_sts_reg;
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u32 ctrl_clock_ena_reg;
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u32 refclk_frequency_mhz;
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u8 sas_addr[SAS_ADDR_SIZE];
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int n_phy;
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spinlock_t lock;
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struct timer_list timer;
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struct workqueue_struct *wq;
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int slot_index_count;
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unsigned long *slot_index_tags;
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unsigned long reject_stp_links_msk;
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/* SCSI/SAS glue */
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struct sas_ha_struct sha;
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struct Scsi_Host *shost;
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struct hisi_sas_cq cq[HISI_SAS_MAX_QUEUES];
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struct hisi_sas_dq dq[HISI_SAS_MAX_QUEUES];
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struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS];
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struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
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int queue_count;
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struct dma_pool *buffer_pool;
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struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES];
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struct hisi_sas_cmd_hdr *cmd_hdr[HISI_SAS_MAX_QUEUES];
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dma_addr_t cmd_hdr_dma[HISI_SAS_MAX_QUEUES];
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void *complete_hdr[HISI_SAS_MAX_QUEUES];
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dma_addr_t complete_hdr_dma[HISI_SAS_MAX_QUEUES];
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struct hisi_sas_initial_fis *initial_fis;
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dma_addr_t initial_fis_dma;
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struct hisi_sas_itct *itct;
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dma_addr_t itct_dma;
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struct hisi_sas_iost *iost;
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dma_addr_t iost_dma;
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struct hisi_sas_breakpoint *breakpoint;
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dma_addr_t breakpoint_dma;
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struct hisi_sas_breakpoint *sata_breakpoint;
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dma_addr_t sata_breakpoint_dma;
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struct hisi_sas_slot *slot_info;
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unsigned long flags;
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const struct hisi_sas_hw *hw; /* Low level hw interface */
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unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)];
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struct work_struct rst_work;
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};
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/* Generic HW DMA host memory structures */
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/* Delivery queue header */
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struct hisi_sas_cmd_hdr {
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/* dw0 */
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__le32 dw0;
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/* dw1 */
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__le32 dw1;
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/* dw2 */
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__le32 dw2;
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/* dw3 */
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__le32 transfer_tags;
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/* dw4 */
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__le32 data_transfer_len;
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/* dw5 */
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__le32 first_burst_num;
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/* dw6 */
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__le32 sg_len;
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/* dw7 */
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__le32 dw7;
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/* dw8-9 */
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__le64 cmd_table_addr;
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/* dw10-11 */
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__le64 sts_buffer_addr;
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/* dw12-13 */
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__le64 prd_table_addr;
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/* dw14-15 */
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__le64 dif_prd_table_addr;
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};
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struct hisi_sas_itct {
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__le64 qw0;
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__le64 sas_addr;
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__le64 qw2;
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__le64 qw3;
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__le64 qw4_15[12];
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};
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struct hisi_sas_iost {
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__le64 qw0;
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__le64 qw1;
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__le64 qw2;
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__le64 qw3;
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};
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struct hisi_sas_err_record {
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u32 data[4];
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};
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struct hisi_sas_initial_fis {
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struct hisi_sas_err_record err_record;
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struct dev_to_host_fis fis;
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u32 rsvd[3];
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};
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struct hisi_sas_breakpoint {
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u8 data[128];
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};
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struct hisi_sas_sata_breakpoint {
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struct hisi_sas_breakpoint tag[32];
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};
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struct hisi_sas_sge {
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__le64 addr;
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__le32 page_ctrl_0;
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__le32 page_ctrl_1;
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__le32 data_len;
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__le32 data_off;
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};
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struct hisi_sas_command_table_smp {
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u8 bytes[44];
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};
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struct hisi_sas_command_table_stp {
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struct host_to_dev_fis command_fis;
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u8 dummy[12];
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u8 atapi_cdb[ATAPI_CDB_LEN];
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};
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#define HISI_SAS_SGE_PAGE_CNT SG_CHUNK_SIZE
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struct hisi_sas_sge_page {
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struct hisi_sas_sge sge[HISI_SAS_SGE_PAGE_CNT];
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} __aligned(16);
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struct hisi_sas_command_table_ssp {
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struct ssp_frame_hdr hdr;
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union {
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struct {
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struct ssp_command_iu task;
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u32 prot[6];
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};
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struct ssp_tmf_iu ssp_task;
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struct xfer_rdy_iu xfer_rdy;
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struct ssp_response_iu ssp_res;
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} u;
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};
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union hisi_sas_command_table {
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struct hisi_sas_command_table_ssp ssp;
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struct hisi_sas_command_table_smp smp;
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struct hisi_sas_command_table_stp stp;
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} __aligned(16);
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struct hisi_sas_status_buffer {
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struct hisi_sas_err_record err;
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u8 iu[1024];
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} __aligned(16);
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struct hisi_sas_slot_buf_table {
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struct hisi_sas_status_buffer status_buffer;
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union hisi_sas_command_table command_header;
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struct hisi_sas_sge_page sge_page;
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};
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extern struct scsi_transport_template *hisi_sas_stt;
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extern struct scsi_host_template *hisi_sas_sht;
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extern void hisi_sas_stop_phys(struct hisi_hba *hisi_hba);
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extern void hisi_sas_init_add(struct hisi_hba *hisi_hba);
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extern int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost);
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extern void hisi_sas_free(struct hisi_hba *hisi_hba);
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extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction);
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extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
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extern void hisi_sas_sata_done(struct sas_task *task,
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struct hisi_sas_slot *slot);
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extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag);
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extern int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba);
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extern int hisi_sas_probe(struct platform_device *pdev,
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const struct hisi_sas_hw *ops);
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extern int hisi_sas_remove(struct platform_device *pdev);
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extern void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy);
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extern void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba,
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struct sas_task *task,
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struct hisi_sas_slot *slot);
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extern void hisi_sas_init_mem(struct hisi_hba *hisi_hba);
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extern void hisi_sas_rst_work_handler(struct work_struct *work);
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extern void hisi_sas_sync_rst_work_handler(struct work_struct *work);
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extern void hisi_sas_kill_tasklets(struct hisi_hba *hisi_hba);
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#endif
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