Thierry Reding 720ad00ead dt-bindings: memory: Add Tegra186 memory subsystem ... The NVIDIA Tegra186 SoC contains a memory subsystem composed of the memory controller and the external memory controller. The memory controller provides interfaces for the memory clients to access the memory. Accesses can be either bounced through the SMMU for IOVA translation or directly to the EMC. The bulk of the programming of the external memory controller happens through interfaces exposed by the BPMP. Describe this relationship by adding a phandle reference to the BPMP to the EMC node. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org>		2020-01-09 19:11:26 +01:00
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bindings	dt-bindings: memory: Add Tegra186 memory subsystem	2020-01-09 19:11:26 +01:00
booting-without-of.txt
changesets.txt
dynamic-resolution-notes.txt
of_unittest.txt
overlay-notes.txt
usage-model.txt
writing-schema.rst	dt-bindings: Improve validation build error handling	2019-11-14 10:46:16 -06:00