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Add the compatible string for Meson8b in Meson pinctrl documentation and add new information for Meson8b in source code comments. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
97 lines
2.7 KiB
Plaintext
97 lines
2.7 KiB
Plaintext
== Amlogic Meson pinmux controller ==
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Required properties for the root node:
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- compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl"
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- reg: address and size of registers controlling irq functionality
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=== GPIO sub-nodes ===
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The 2 power domains of the controller (regular and always-on) are
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represented as sub-nodes and each of them acts as a GPIO controller.
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Required properties for sub-nodes are:
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- reg: should contain address and size for mux, pull-enable, pull and
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gpio register sets
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- reg-names: an array of strings describing the "reg" entries. Must
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contain "mux", "pull" and "gpio". "pull-enable" is optional and
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when it is missing the "pull" registers are used instead
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- gpio-controller: identifies the node as a gpio controller
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- #gpio-cells: must be 2
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Valid sub-node names are:
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- "banks" for the regular domain
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- "ao-bank" for the always-on domain
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=== Other sub-nodes ===
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Child nodes without the "gpio-controller" represent some desired
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configuration for a pin or a group. Those nodes can be pinmux nodes or
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configuration nodes.
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Required properties for pinmux nodes are:
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- groups: a list of pinmux groups. The list of all available groups
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depends on the SoC and can be found in driver sources.
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- function: the name of a function to activate for the specified set
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of groups. The list of all available functions depends on the SoC
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and can be found in driver sources.
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Required properties for configuration nodes:
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- pins: a list of pin names
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Configuration nodes support the generic properties "bias-disable",
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"bias-pull-up" and "bias-pull-down", described in file
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pinctrl-bindings.txt
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=== Example ===
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pinctrl: pinctrl@c1109880 {
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compatible = "amlogic,meson8-pinctrl";
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reg = <0xc1109880 0x10>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio: banks@c11080b0 {
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reg = <0xc11080b0 0x28>,
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<0xc11080e8 0x18>,
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<0xc1108120 0x18>,
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<0xc1108030 0x30>;
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio_ao: ao-bank@c1108030 {
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reg = <0xc8100014 0x4>,
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<0xc810002c 0x4>,
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<0xc8100024 0x8>;
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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nand {
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mux {
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groups = "nand_io", "nand_io_ce0", "nand_io_ce1",
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"nand_io_rb0", "nand_ale", "nand_cle",
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"nand_wen_clk", "nand_ren_clk", "nand_dqs",
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"nand_ce2", "nand_ce3";
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function = "nand";
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};
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};
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uart_ao_a {
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mux {
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groups = "uart_tx_ao_a", "uart_rx_ao_a",
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"uart_cts_ao_a", "uart_rts_ao_a";
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function = "uart_ao";
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};
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conf {
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pins = "GPIOAO_0", "GPIOAO_1",
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"GPIOAO_2", "GPIOAO_3";
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bias-disable;
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};
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};
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};
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