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a93f1d903f
This controller appeared on Loongson-3 family of chips to receive interrupts from PCH PIC. It is a I8259 with optimized interrupt polling flow. We can poll interrupt number from HT vector directly but still have to follow standard I8259 routines to mask, unmask and EOI. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Co-developed-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
150 lines
3.0 KiB
C
150 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
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* Loongson HTPIC IRQ support
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*/
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <asm/i8259.h>
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#define HTPIC_MAX_PARENT_IRQ 4
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#define HTINT_NUM_VECTORS 8
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#define HTINT_EN_OFF 0x20
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struct loongson_htpic {
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void __iomem *base;
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struct irq_domain *domain;
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};
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static struct loongson_htpic *htpic;
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static void htpic_irq_dispatch(struct irq_desc *desc)
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{
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struct loongson_htpic *priv = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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uint32_t pending;
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chained_irq_enter(chip, desc);
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pending = readl(priv->base);
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/* Ack all IRQs at once, otherwise IRQ flood might happen */
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writel(pending, priv->base);
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if (!pending)
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spurious_interrupt();
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while (pending) {
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int bit = __ffs(pending);
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if (unlikely(bit > 15)) {
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spurious_interrupt();
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break;
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}
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generic_handle_irq(irq_linear_revmap(priv->domain, bit));
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pending &= ~BIT(bit);
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}
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chained_irq_exit(chip, desc);
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}
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static void htpic_reg_init(void)
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{
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int i;
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for (i = 0; i < HTINT_NUM_VECTORS; i++) {
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uint32_t val;
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/* Disable all HT Vectors */
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writel(0x0, htpic->base + HTINT_EN_OFF + i * 0x4);
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val = readl(htpic->base + i * 0x4);
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/* Ack all possible pending IRQs */
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writel(GENMASK(31, 0), htpic->base + i * 0x4);
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}
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/* Enable 16 vectors for PIC */
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writel(0xffff, htpic->base + HTINT_EN_OFF);
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}
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static void htpic_resume(void)
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{
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htpic_reg_init();
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}
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struct syscore_ops htpic_syscore_ops = {
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.resume = htpic_resume,
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};
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int __init htpic_of_init(struct device_node *node, struct device_node *parent)
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{
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unsigned int parent_irq[4];
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int i, err;
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int num_parents = 0;
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if (htpic) {
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pr_err("loongson-htpic: Only one HTPIC is allowed in the system\n");
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return -ENODEV;
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}
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htpic = kzalloc(sizeof(*htpic), GFP_KERNEL);
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if (!htpic) {
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err = -ENOMEM;
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goto out_free;
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}
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htpic->base = of_iomap(node, 0);
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if (!htpic->base) {
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err = -ENODEV;
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goto out_free;
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}
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htpic->domain = __init_i8259_irqs(node);
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if (!htpic->domain) {
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pr_err("loongson-htpic: Failed to initialize i8259 IRQs\n");
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err = -ENOMEM;
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goto out_iounmap;
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}
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/* Interrupt may come from any of the 4 interrupt line */
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for (i = 0; i < HTPIC_MAX_PARENT_IRQ; i++) {
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parent_irq[i] = irq_of_parse_and_map(node, i);
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if (parent_irq[i] <= 0)
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break;
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num_parents++;
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}
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if (!num_parents) {
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pr_err("loongson-htpic: Failed to get parent irqs\n");
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err = -ENODEV;
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goto out_remove_domain;
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}
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htpic_reg_init();
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for (i = 0; i < num_parents; i++) {
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irq_set_chained_handler_and_data(parent_irq[i],
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htpic_irq_dispatch, htpic);
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}
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register_syscore_ops(&htpic_syscore_ops);
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return 0;
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out_remove_domain:
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irq_domain_remove(htpic->domain);
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out_iounmap:
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iounmap(htpic->base);
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out_free:
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kfree(htpic);
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return err;
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}
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IRQCHIP_DECLARE(loongson_htpic, "loongson,htpic-1.0", htpic_of_init);
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