mirror of
https://github.com/torvalds/linux.git
synced 2024-12-04 10:01:41 +00:00
712424fd95
On pre-A0 revisions of the mv78xx0 SoC, the third and fourth ethernet interface are not brought out to pins, but are internally cross-connected, so if we run on pre-A0 silicon, we'll force eth2 and eth3 to PHYless mode. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> |
||
---|---|---|
.. | ||
include/mach | ||
addr-map.c | ||
common.c | ||
common.h | ||
db78x00-bp-setup.c | ||
irq.c | ||
Kconfig | ||
Makefile | ||
Makefile.boot | ||
pcie.c |