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Add documentation for the new Perf event open parameters and the threshold_max capability file. Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Acked-by: Namhyung Kim <namhyung@kernel.org> Signed-off-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20231211161331.1277825-12-james.clark@arm.com Signed-off-by: Will Deacon <will@kernel.org>
239 lines
8.3 KiB
ReStructuredText
239 lines
8.3 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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.. _perf_index:
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====
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Perf
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====
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Perf Event Attributes
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=====================
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:Author: Andrew Murray <andrew.murray@arm.com>
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:Date: 2019-03-06
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exclude_user
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------------
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This attribute excludes userspace.
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Userspace always runs at EL0 and thus this attribute will exclude EL0.
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exclude_kernel
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--------------
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This attribute excludes the kernel.
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The kernel runs at EL2 with VHE and EL1 without. Guest kernels always run
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at EL1.
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For the host this attribute will exclude EL1 and additionally EL2 on a VHE
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system.
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For the guest this attribute will exclude EL1. Please note that EL2 is
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never counted within a guest.
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exclude_hv
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----------
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This attribute excludes the hypervisor.
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For a VHE host this attribute is ignored as we consider the host kernel to
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be the hypervisor.
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For a non-VHE host this attribute will exclude EL2 as we consider the
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hypervisor to be any code that runs at EL2 which is predominantly used for
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guest/host transitions.
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For the guest this attribute has no effect. Please note that EL2 is
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never counted within a guest.
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exclude_host / exclude_guest
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----------------------------
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These attributes exclude the KVM host and guest, respectively.
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The KVM host may run at EL0 (userspace), EL1 (non-VHE kernel) and EL2 (VHE
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kernel or non-VHE hypervisor).
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The KVM guest may run at EL0 (userspace) and EL1 (kernel).
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Due to the overlapping exception levels between host and guests we cannot
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exclusively rely on the PMU's hardware exception filtering - therefore we
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must enable/disable counting on the entry and exit to the guest. This is
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performed differently on VHE and non-VHE systems.
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For non-VHE systems we exclude EL2 for exclude_host - upon entering and
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exiting the guest we disable/enable the event as appropriate based on the
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exclude_host and exclude_guest attributes.
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For VHE systems we exclude EL1 for exclude_guest and exclude both EL0,EL2
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for exclude_host. Upon entering and exiting the guest we modify the event
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to include/exclude EL0 as appropriate based on the exclude_host and
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exclude_guest attributes.
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The statements above also apply when these attributes are used within a
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non-VHE guest however please note that EL2 is never counted within a guest.
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Accuracy
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--------
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On non-VHE hosts we enable/disable counters on the entry/exit of host/guest
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transition at EL2 - however there is a period of time between
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enabling/disabling the counters and entering/exiting the guest. We are
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able to eliminate counters counting host events on the boundaries of guest
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entry/exit when counting guest events by filtering out EL2 for
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exclude_host. However when using !exclude_hv there is a small blackout
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window at the guest entry/exit where host events are not captured.
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On VHE systems there are no blackout windows.
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Perf Userspace PMU Hardware Counter Access
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==========================================
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Overview
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--------
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The perf userspace tool relies on the PMU to monitor events. It offers an
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abstraction layer over the hardware counters since the underlying
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implementation is cpu-dependent.
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Arm64 allows userspace tools to have access to the registers storing the
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hardware counters' values directly.
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This targets specifically self-monitoring tasks in order to reduce the overhead
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by directly accessing the registers without having to go through the kernel.
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How-to
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------
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The focus is set on the armv8 PMUv3 which makes sure that the access to the pmu
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registers is enabled and that the userspace has access to the relevant
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information in order to use them.
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In order to have access to the hardware counters, the global sysctl
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kernel/perf_user_access must first be enabled:
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.. code-block:: sh
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echo 1 > /proc/sys/kernel/perf_user_access
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It is necessary to open the event using the perf tool interface with config1:1
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attr bit set: the sys_perf_event_open syscall returns a fd which can
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subsequently be used with the mmap syscall in order to retrieve a page of memory
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containing information about the event. The PMU driver uses this page to expose
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to the user the hardware counter's index and other necessary data. Using this
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index enables the user to access the PMU registers using the `mrs` instruction.
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Access to the PMU registers is only valid while the sequence lock is unchanged.
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In particular, the PMSELR_EL0 register is zeroed each time the sequence lock is
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changed.
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The userspace access is supported in libperf using the perf_evsel__mmap()
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and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for
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an example.
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About heterogeneous systems
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---------------------------
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On heterogeneous systems such as big.LITTLE, userspace PMU counter access can
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only be enabled when the tasks are pinned to a homogeneous subset of cores and
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the corresponding PMU instance is opened by specifying the 'type' attribute.
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The use of generic event types is not supported in this case.
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Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It
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can be run using the perf tool to check that the access to the registers works
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correctly from userspace:
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.. code-block:: sh
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perf test -v user
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About chained events and counter sizes
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--------------------------------------
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The user can request either a 32-bit (config1:0 == 0) or 64-bit (config1:0 == 1)
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counter along with userspace access. The sys_perf_event_open syscall will fail
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if a 64-bit counter is requested and the hardware doesn't support 64-bit
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counters. Chained events are not supported in conjunction with userspace counter
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access. If a 32-bit counter is requested on hardware with 64-bit counters, then
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userspace must treat the upper 32-bits read from the counter as UNKNOWN. The
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'pmc_width' field in the user page will indicate the valid width of the counter
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and should be used to mask the upper bits as needed.
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.. Links
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.. _tools/perf/arch/arm64/tests/user-events.c:
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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c
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.. _tools/lib/perf/tests/test-evsel.c:
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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c
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Event Counting Threshold
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==========================================
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Overview
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--------
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FEAT_PMUv3_TH (Armv8.8) permits a PMU counter to increment only on
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events whose count meets a specified threshold condition. For example if
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threshold_compare is set to 2 ('Greater than or equal'), and the
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threshold is set to 2, then the PMU counter will now only increment by
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when an event would have previously incremented the PMU counter by 2 or
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more on a single processor cycle.
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To increment by 1 after passing the threshold condition instead of the
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number of events on that cycle, add the 'threshold_count' option to the
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commandline.
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How-to
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------
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These are the parameters for controlling the feature:
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.. list-table::
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:header-rows: 1
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* - Parameter
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- Description
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* - threshold
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- Value to threshold the event by. A value of 0 means that
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thresholding is disabled and the other parameters have no effect.
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* - threshold_compare
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- | Comparison function to use, with the following values supported:
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| 0: Not-equal
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| 1: Equals
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| 2: Greater-than-or-equal
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| 3: Less-than
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* - threshold_count
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- If this is set, count by 1 after passing the threshold condition
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instead of the value of the event on this cycle.
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The threshold, threshold_compare and threshold_count values can be
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provided per event, for example:
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.. code-block:: sh
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perf stat -e stall_slot/threshold=2,threshold_compare=2/ \
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-e dtlb_walk/threshold=10,threshold_compare=3,threshold_count/
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In this example the stall_slot event will count by 2 or more on every
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cycle where 2 or more stalls happen. And dtlb_walk will count by 1 on
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every cycle where the number of dtlb walks were less than 10.
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The maximum supported threshold value can be read from the caps of each
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PMU, for example:
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.. code-block:: sh
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cat /sys/bus/event_source/devices/armv8_pmuv3/caps/threshold_max
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0x000000ff
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If a value higher than this is given, then opening the event will result
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in an error. The highest possible maximum is 4095, as the config field
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for threshold is limited to 12 bits, and the Perf tool will refuse to
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parse higher values.
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If the PMU doesn't support FEAT_PMUv3_TH, then threshold_max will read
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0, and attempting to set a threshold value will also result in an error.
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threshold_max will also read as 0 on aarch32 guests, even if the host
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is running on hardware with the feature.
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