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linux/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
Linus Torvalds c1b30e4d94 Pin control changes for the v3.19 series: 
- Force conversion of the ux500 pin control device trees
   and parsers to use the generic pin control bindings.
 - New driver and device tree bindings for the Qualcomm
   PMIC MPP pin controller and GPIO.
 - Some ACPI infrastructure for pin controllers.
 - New driver for the Intel CherryView/Braswell pin controller,
   the first Intel pin controller to fully take advantage of
   the pin control subsystem.
 - Support the Freescale i.MX VF610 variant.
 - Support the sunxi A80 variant.
 - Support the Samsung Exynos 4415 and Exynos 7 variants.
 - Split out Intel pin controllers to their own subdirectory.
 - A large slew of rockchip pin control updates, including
   suspend/resume support.
 - A large slew of Samsung Exynos pin controller updates.
 - Various minor updates and fixes.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUhrHUAAoJEEEQszewGV1zPZsQAMzWjGKcZhyBDWyTsHM/E9nN
 csRIcVdXs+OggH0nr2YNm2AAh+nRlp4DAQCB7S83SLfKFHF4oWT8SlornEl7WKdN
 zcVUbV29LtHkotjtVoGQZmjuJx+uvHlWJt7moTKJsAMTeNyXv25jEp0LGETji24A
 xsIQ+Bp+G9IYZqK1dlJFPva1YMjjt9sBhJqKnOhh5Z+wjj3YdT7z5LW1x001GPju
 kwKumgxOL7qKjvyaI7n2z+9VhGu9zAvoxK2gLOgjgtFQODASLS/gk2oCuRi/fIpn
 RqE+YyfrNSeMKpOjZOXc/R0SRtOkhyvMBYbgQrAX04nio4pbT6x2XgclAe6v7O5Q
 T3GmOR2JZblwrzEPRs5mGBC9p7fd488ToHAPg5ojNH5F70hDkC8wSYYJZmaL+ORw
 umyxRlRjIbQ4vs6cZMlz/NksqpQyqCTMuBRLllo/jsSQlk0Vo3Gdci5J/T10lKd2
 ciX6AxlRKaRyRo+W6/i01xcX7SzzmNZoOCMXWSjsPv7Th+Gm7vIKyVeNOUkiqUXH
 1fVjw/M0AhIttVRbx1qTPsqFaDI/WPPk9EUvVm3W7DFuf0/w9B0HkZe6KpXdp33K
 GV6gEMvmTObvUpwYrYEi7hhKVl+cJ902ZMR/LSmK0QdADhI98pjsokDrigl+Jy93
 U1OepT70fw4mgJnqnevZ
 =sxpe
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control changes from Linus Walleij:
 "Here is a stash of pin control changes I have collected for the v3.19
  series.  Mainly new hardware support, with Intels new embedded SoC as
  the especially interesting thing standing out, fully using the
  subsystem.

   - Force conversion of the ux500 pin control device trees and parsers
     to use the generic pin control bindings.
   - New driver and device tree bindings for the Qualcomm PMIC MPP pin
     controller and GPIO.
   - Some ACPI infrastructure for pin controllers.
   - New driver for the Intel CherryView/Braswell pin controller, the
     first Intel pin controller to fully take advantage of the pin
     control subsystem.
   - Support the Freescale i.MX VF610 variant.
   - Support the sunxi A80 variant.
   - Support the Samsung Exynos 4415 and Exynos 7 variants.
   - Split out Intel pin controllers to their own subdirectory.
   - A large slew of rockchip pin control updates, including
     suspend/resume support.
   - A large slew of Samsung Exynos pin controller updates.
   - Various minor updates and fixes"

* tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (49 commits)
  pinctrl: at91: enhance (debugfs) at91_gpio_dbg_show
  pinctrl: meson: add device tree bindings documentation
  gpio: tz1090: Fix error handling of irq_of_parse_and_map
  pinctrl: tz1090-pinctrl.txt: Fix typo in binding
  pinctrl: pinconf-generic: Declare dt_params/conf_items const
  pinctrl: exynos: Add support for Exynos4415
  pinctrl: exynos: Add initial driver data for Exynos7
  pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
  pinctrl: exynos: Consolidate irq domain callbacks
  pinctrl: exynos: Generalize the eint16_31 demux code
  pinctrl: samsung: Separate per-bank init and runtime data
  pinctrl: samsung: Constify samsung_pin_ctrl struct
  pinctrl: samsung: Constify samsung_pin_bank_type struct
  pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct
  pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR()
  pinctrl: Add Intel Cherryview/Braswell pin controller support
  gpio / ACPI: Add knowledge about pin controllers to acpi_get_gpiod()
  pinctrl: Fix path error in documentation
  pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
  pinctrl: rockchip: add suspend/resume functions
  ...
2014-12-11 10:43:14 -08:00

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/*
* Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
*/
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0x00000000 0x04000000>,
<0x08000000 0x04000000>;
};
L2: l2-cache {
compatible = "arm,l210-cache";
reg = <0x10210000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <30>;
cache-unified;
cache-level = <2>;
};
mtu0: mtu@101e2000 {
/* Nomadik system timer */
compatible = "st,nomadik-mtu";
reg = <0x101e2000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <4>;
clocks = <&timclk>, <&pclk>;
clock-names = "timclk", "apb_pclk";
};
mtu1: mtu@101e3000 {
/* Secondary timer */
reg = <0x101e3000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <5>;
clocks = <&timclk>, <&pclk>;
clock-names = "timclk", "apb_pclk";
};
gpio0: gpio@101e4000 {
compatible = "st,nomadik-gpio";
reg = <0x101e4000 0x80>;
interrupt-parent = <&vica>;
interrupts = <6>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <0>;
clocks = <&pclk>;
};
gpio1: gpio@101e5000 {
compatible = "st,nomadik-gpio";
reg = <0x101e5000 0x80>;
interrupt-parent = <&vica>;
interrupts = <7>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <1>;
clocks = <&pclk>;
};
gpio2: gpio@101e6000 {
compatible = "st,nomadik-gpio";
reg = <0x101e6000 0x80>;
interrupt-parent = <&vica>;
interrupts = <8>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <2>;
clocks = <&pclk>;
};
gpio3: gpio@101e7000 {
compatible = "st,nomadik-gpio";
reg = <0x101e7000 0x80>;
interrupt-parent = <&vica>;
interrupts = <9>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <3>;
clocks = <&pclk>;
};
pinctrl {
compatible = "stericsson,stn8815-pinctrl";
/* Pin configurations */
uart0 {
uart0_default_mux: uart0_mux {
u0_default_mux {
function = "u0";
groups = "u0_a_1";
};
};
};
uart1 {
uart1_default_mux: uart1_mux {
u1_default_mux {
function = "u1";
groups = "u1_a_1";
};
};
};
mmcsd {
mmcsd_default_mux: mmcsd_mux {
mmcsd_default_mux {
function = "mmcsd";
groups = "mmcsd_a_1", "mmcsd_b_1";
};
};
mmcsd_default_mode: mmcsd_default {
mmcsd_default_cfg1 {
/* MCCLK */
pins = "GPIO8_B10";
ste,output = <0>;
};
mmcsd_default_cfg2 {
/* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */
pins = "GPIO10_C11", "GPIO15_A12",
"GPIO16_C13", "GPIO23_D15";
ste,output = <1>;
};
mmcsd_default_cfg3 {
/* MCCMD, MCDAT3-0, MCMSFBCLK */
pins = "GPIO9_A10", "GPIO11_B11",
"GPIO12_A11", "GPIO13_C12",
"GPIO14_B12", "GPIO24_C15";
ste,input = <1>;
};
};
};
i2c0 {
i2c0_default_mux: i2c0_mux {
i2c0_default_mux {
function = "i2c0";
groups = "i2c0_a_1";
};
};
i2c0_default_mode: i2c0_default {
i2c0_default_cfg {
pins = "GPIO62_D3", "GPIO63_D2";
ste,input = <0>;
};
};
};
i2c1 {
i2c1_default_mux: i2c1_mux {
i2c1_default_mux {
function = "i2c1";
groups = "i2c1_a_1";
};
};
i2c1_default_mode: i2c1_default {
i2c1_default_cfg {
pins = "GPIO53_L4", "GPIO54_L3";
ste,input = <0>;
};
};
};
};
src: src@101e0000 {
compatible = "stericsson,nomadik-src";
reg = <0x101e0000 0x1000>;
/*
* MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
* that is parent of TIMCLK, PLL1 and PLL2
*/
mxtal: mxtal@19.2M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <19200000>;
};
/*
* The 2.4 MHz TIMCLK reference clock is active at
* boot time, this is actually the MXTALCLK @19.2 MHz
* divided by 8. This clock is used by the timers and
* watchdog. See page 105 ff.
*/
timclk: timclk@2.4M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <8>;
clock-mult = <1>;
clocks = <&mxtal>;
};
/* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
pll1: pll1@0 {
#clock-cells = <0>;
compatible = "st,nomadik-pll-clock";
pll-id = <1>;
clocks = <&mxtal>;
};
/* HCLK divides the PLL1 with 1,2,3 or 4 */
hclk: hclk@0 {
#clock-cells = <0>;
compatible = "st,nomadik-hclk-clock";
clocks = <&pll1>;
};
/* The PCLK domain uses HCLK right off */
pclk: pclk@0 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&hclk>;
};
/* PLL2 is usually 864 MHz and divided into a few fixed rates */
pll2: pll2@0 {
#clock-cells = <0>;
compatible = "st,nomadik-pll-clock";
pll-id = <2>;
clocks = <&mxtal>;
};
clk216: clk216@216M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <4>;
clock-mult = <1>;
clocks = <&pll2>;
};
clk108: clk108@108M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
clock-mult = <1>;
clocks = <&clk216>;
};
clk72: clk72@72M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
/* The data sheet does not say how this is derived */
clock-div = <12>;
clock-mult = <1>;
clocks = <&pll2>;
};
clk48: clk48@48M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
/* The data sheet does not say how this is derived */
clock-div = <18>;
clock-mult = <1>;
clocks = <&pll2>;
};
clk27: clk27@27M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <4>;
clock-mult = <1>;
clocks = <&clk108>;
};
/* This apparently exists as well */
ulpiclk: ulpiclk@60M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <60000000>;
};
/*
* IP AMBA bus clocks, driving the bus side of the
* peripheral clocking, clock gates.
*/
hclkdma0: hclkdma0@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <0>;
clocks = <&hclk>;
};
hclksmc: hclksmc@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <1>;
clocks = <&hclk>;
};
hclksdram: hclksdram@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <2>;
clocks = <&hclk>;
};
hclkdma1: hclkdma1@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <3>;
clocks = <&hclk>;
};
hclkclcd: hclkclcd@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <4>;
clocks = <&hclk>;
};
pclkirda: pclkirda@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <5>;
clocks = <&pclk>;
};
pclkssp: pclkssp@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <6>;
clocks = <&pclk>;
};
pclkuart0: pclkuart0@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <7>;
clocks = <&pclk>;
};
pclksdi: pclksdi@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <8>;
clocks = <&pclk>;
};
pclki2c0: pclki2c0@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <9>;
clocks = <&pclk>;
};
pclki2c1: pclki2c1@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <10>;
clocks = <&pclk>;
};
pclkuart1: pclkuart1@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <11>;
clocks = <&pclk>;
};
pclkmsp0: pclkmsp0@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <12>;
clocks = <&pclk>;
};
hclkusb: hclkusb@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <13>;
clocks = <&hclk>;
};
hclkdif: hclkdif@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <14>;
clocks = <&hclk>;
};
hclksaa: hclksaa@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <15>;
clocks = <&hclk>;
};
hclksva: hclksva@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <16>;
clocks = <&hclk>;
};
pclkhsi: pclkhsi@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <17>;
clocks = <&pclk>;
};
pclkxti: pclkxti@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <18>;
clocks = <&pclk>;
};
pclkuart2: pclkuart2@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <19>;
clocks = <&pclk>;
};
pclkmsp1: pclkmsp1@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <20>;
clocks = <&pclk>;
};
pclkmsp2: pclkmsp2@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <21>;
clocks = <&pclk>;
};
pclkowm: pclkowm@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <22>;
clocks = <&pclk>;
};
hclkhpi: hclkhpi@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <23>;
clocks = <&hclk>;
};
pclkske: pclkske@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <24>;
clocks = <&pclk>;
};
pclkhsem: pclkhsem@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <25>;
clocks = <&pclk>;
};
hclk3d: hclk3d@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <26>;
clocks = <&hclk>;
};
hclkhash: hclkhash@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <27>;
clocks = <&hclk>;
};
hclkcryp: hclkcryp@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <28>;
clocks = <&hclk>;
};
pclkmshc: pclkmshc@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <29>;
clocks = <&pclk>;
};
hclkusbm: hclkusbm@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <30>;
clocks = <&hclk>;
};
hclkrng: hclkrng@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <31>;
clocks = <&hclk>;
};
/* IP kernel clocks */
clcdclk: clcdclk@0 {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <36>;
clocks = <&clk72 &clk48>;
};
irdaclk: irdaclk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <37>;
clocks = <&clk48>;
};
sspiclk: sspiclk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <38>;
clocks = <&clk48>;
};
uart0clk: uart0clk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <39>;
clocks = <&clk48>;
};
sdiclk: sdiclk@48M {
/* Also called MCCLK in some documents */
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <40>;
clocks = <&clk48>;
};
i2c0clk: i2c0clk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <41>;
clocks = <&clk48>;
};
i2c1clk: i2c1clk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <42>;
clocks = <&clk48>;
};
uart1clk: uart1clk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <43>;
clocks = <&clk48>;
};
mspclk0: mspclk0@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <44>;
clocks = <&clk48>;
};
usbclk: usbclk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <45>;
clocks = <&clk48>; /* 48 MHz not ULPI */
};
difclk: difclk@72M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <46>;
clocks = <&clk72>;
};
ipi2cclk: ipi2cclk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <47>;
clocks = <&clk48>; /* Guess */
};
ipbmcclk: ipbmcclk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <48>;
clocks = <&clk48>; /* Guess */
};
hsiclkrx: hsiclkrx@216M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <49>;
clocks = <&clk216>;
};
hsiclktx: hsiclktx@108M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <50>;
clocks = <&clk108>;
};
uart2clk: uart2clk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <51>;
clocks = <&clk48>;
};
mspclk1: mspclk1@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <52>;
clocks = <&clk48>;
};
mspclk2: mspclk2@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <53>;
clocks = <&clk48>;
};
owmclk: owmclk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <54>;
clocks = <&clk48>; /* Guess */
};
skeclk: skeclk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <56>;
clocks = <&clk48>; /* Guess */
};
x3dclk: x3dclk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <58>;
clocks = <&clk48>; /* Guess */
};
pclkmsp3: pclkmsp3@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <59>;
clocks = <&pclk>;
};
mspclk3: mspclk3@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <60>;
clocks = <&clk48>;
};
mshcclk: mshcclk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <61>;
clocks = <&clk48>; /* Guess */
};
usbmclk: usbmclk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <62>;
/* Stated as "48 MHz not ULPI clock" */
clocks = <&clk48>;
};
rngcclk: rngcclk@48M {
#clock-cells = <0>;
compatible = "st,nomadik-src-clock";
clock-id = <63>;
clocks = <&clk48>; /* Guess */
};
};
/* A NAND flash of 128 MiB */
fsmc: flash@40000000 {
compatible = "stericsson,fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x10100000 0x1000>, /* FSMC Register*/
<0x40000000 0x2000>, /* NAND Base DATA */
<0x41000000 0x2000>, /* NAND Base ADDR */
<0x40800000 0x2000>; /* NAND Base CMD */
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
clocks = <&hclksmc>;
status = "okay";
timings = /bits/ 8 <0 0 0 0x10 0x0a 0>;
partition@0 {
label = "X-Loader(NAND)";
reg = <0x0 0x40000>;
};
partition@40000 {
label = "MemInit(NAND)";
reg = <0x40000 0x40000>;
};
partition@80000 {
label = "BootLoader(NAND)";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "Kernel zImage(NAND)";
reg = <0x280000 0x300000>;
};
partition@580000 {
label = "Root Filesystem(NAND)";
reg = <0x580000 0x1600000>;
};
partition@1b80000 {
label = "User Filesystem(NAND)";
reg = <0x1b80000 0x6480000>;
};
};
/* I2C0 connected to the STw4811 power management chip */
i2c0 {
compatible = "st,nomadik-i2c", "arm,primecell";
reg = <0x101f8000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <20>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&i2c0clk>, <&pclki2c0>;
clock-names = "mclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>;
stw4811@2d {
compatible = "st,stw4811";
reg = <0x2d>;
vmmc_regulator: vmmc {
compatible = "st,stw481x-vmmc";
regulator-name = "VMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
/* I2C1 connected to various sensors */
i2c1 {
compatible = "st,nomadik-i2c", "arm,primecell";
reg = <0x101f7000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <21>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&i2c1clk>, <&pclki2c1>;
clock-names = "mclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>;
camera@2d {
compatible = "st,camera";
reg = <0x10>;
};
stw5095@1a {
compatible = "st,stw5095";
reg = <0x1a>;
};
lis3lv02dl@1d {
compatible = "st,lis3lv02dl";
reg = <0x1d>;
};
};
amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
vica: intc@10140000 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10140000 0x20>;
};
vicb: intc@10140020 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10140020 0x20>;
};
uart0: uart@101fd000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101fd000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <12>;
clocks = <&uart0clk>, <&pclkuart0>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart0_default_mux>;
};
uart1: uart@101fb000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101fb000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <17>;
clocks = <&uart1clk>, <&pclkuart1>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart1_default_mux>;
};
uart2: uart@101f2000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f2000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <28>;
clocks = <&uart2clk>, <&pclkuart2>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
rng: rng@101b0000 {
compatible = "arm,primecell";
reg = <0x101b0000 0x1000>;
clocks = <&rngcclk>, <&hclkrng>;
clock-names = "rng", "apb_pclk";
};
rtc: rtc@101e8000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x101e8000 0x1000>;
clocks = <&pclk>;
clock-names = "apb_pclk";
interrupt-parent = <&vica>;
interrupts = <10>;
};
mmcsd: sdi@101f6000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x101f6000 0x1000>;
clocks = <&sdiclk>, <&pclksdi>;
clock-names = "mclk", "apb_pclk";
interrupt-parent = <&vica>;
interrupts = <22>;
max-frequency = <48000000>;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
pinctrl-names = "default";
pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
vmmc-supply = <&vmmc_regulator>;
};
};
};
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