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6f69c7f21c
Preparation step for next changes. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
113 lines
3.0 KiB
C
113 lines
3.0 KiB
C
/*
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* Xilinx SLCR driver
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*
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* Copyright (c) 2011-2013 Xilinx Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public
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* License along with this program; if not, write to the Free
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* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
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* 02139, USA.
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*/
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/clk/zynq.h>
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#include "common.h"
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/* register offsets */
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#define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
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#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
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#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
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#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
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#define SLCR_UNLOCK_MAGIC 0xDF0D
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#define SLCR_A9_CPU_CLKSTOP 0x10
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#define SLCR_A9_CPU_RST 0x1
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void __iomem *zynq_slcr_base;
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/**
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* zynq_slcr_system_reset - Reset the entire system.
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*/
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void zynq_slcr_system_reset(void)
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{
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u32 reboot;
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/*
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* Unlock the SLCR then reset the system.
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* Note that this seems to require raw i/o
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* functions or there's a lockup?
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*/
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writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
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/*
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* Clear 0x0F000000 bits of reboot status register to workaround
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* the FSBL not loading the bitstream after soft-reboot
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* This is a temporary solution until we know more.
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*/
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reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
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writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
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writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
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}
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/**
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* zynq_slcr_cpu_start - Start cpu
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* @cpu: cpu number
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*/
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void zynq_slcr_cpu_start(int cpu)
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{
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u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg &= ~(SLCR_A9_CPU_RST << cpu);
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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}
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/**
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* zynq_slcr_cpu_stop - Stop cpu
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* @cpu: cpu number
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*/
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void zynq_slcr_cpu_stop(int cpu)
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{
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u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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}
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/**
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* zynq_slcr_init
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* Returns 0 on success, negative errno otherwise.
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*
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* Called early during boot from platform code to remap SLCR area.
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*/
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int __init zynq_slcr_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
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if (!np) {
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pr_err("%s: no slcr node found\n", __func__);
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BUG();
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}
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zynq_slcr_base = of_iomap(np, 0);
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if (!zynq_slcr_base) {
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pr_err("%s: Unable to map I/O memory\n", __func__);
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BUG();
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}
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/* unlock the SLCR so that registers can be changed */
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writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
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pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
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of_node_put(np);
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return 0;
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}
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