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Once the new configuration is set on the conifg register of I2C controller, it is require to update the CONFIG_LOAD register to transfer the new SW configuration to actual HW internal registers that would be used in the actual logic. It is like, SW is programming only shadow registers through regular configuration and when these load_config bit fields are set to 1, it causes the regular/shadows registers configuration transferred to the HW internal active registers. So SW has to set these bit fields at the end of all regular registers configuration. And these config_load bits are HW auto-clear bits. HW clears these bit fields once the register configuration is moved to HW internal active registers. So SW has to wait until these bits are auto-cleared before going for any further programming This mechanism is supported on T124 and after this SoCs. Signed-off-by: Chaitanya Bandi <bandik@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> |
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| .. | ||
| algos | ||
| busses | ||
| muxes | ||
| i2c-boardinfo.c | ||
| i2c-core.c | ||
| i2c-core.h | ||
| i2c-dev.c | ||
| i2c-mux.c | ||
| i2c-slave-eeprom.c | ||
| i2c-smbus.c | ||
| i2c-stub.c | ||
| Kconfig | ||
| Makefile | ||