linux/arch/arm64/mm
Matthew Leach fc18047c73 arm64: use correct register width when retrieving ASID
The ASID is represented as an unsigned int in mm_context_t and we
currently use the mmid assembler macro to access this element of the
struct. This should be accessed with a register of 32-bit width. If
the incorrect register width is used the ASID will be returned in
bits[32:63] of the register when running under big-endian.

Fix a use of the mmid macro in tlb.S to use a 32-bit access.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-09-25 16:42:23 +01:00
..
cache.S arm64: mm: Fix operands of clz in __flush_dcache_all 2013-05-14 15:44:50 +01:00
context.c arm64: Process management 2012-09-17 13:41:58 +01:00
copypage.c arm64: MMU fault handling and page table management 2012-09-17 13:41:57 +01:00
dma-mapping.c arm64: Call swiotlb_init() instead of swiotlb_init_with_default_size() 2012-10-08 16:02:09 +01:00
extable.c arm64: MMU fault handling and page table management 2012-09-17 13:41:57 +01:00
fault.c arm64: Make do_bad_area() function static 2013-09-20 09:56:05 +01:00
flush.c arm64: Remove __flush_dcache_page() 2013-06-07 17:58:30 +01:00
hugetlbpage.c mm: migrate: check movability of hugepage in unmap_and_move_huge_page() 2013-09-11 15:57:49 -07:00
init.c of: Specify initrd location using 64-bit 2013-07-24 11:10:01 +01:00
ioremap.c arm64: Device specific operations 2012-09-17 13:42:04 +01:00
Makefile ARM64: mm: HugeTLB support. 2013-06-14 09:52:40 +01:00
mm.h arm64: Remove __flush_dcache_page() 2013-06-07 17:58:30 +01:00
mmap.c mm: remove free_area_cache 2013-07-10 18:11:34 -07:00
mmu.c arm64: Fix mapping of memory banks not ending on a PMD_SIZE boundary 2013-08-28 10:47:00 +01:00
pgd.c arm64: MMU fault handling and page table management 2012-09-17 13:41:57 +01:00
proc-macros.S arm64: Assembly macros and definitions 2012-09-17 10:24:44 +01:00
proc.S arm64: mm: permit use of tagged pointers at EL0 2013-09-03 10:18:02 +01:00
tlb.S arm64: use correct register width when retrieving ASID 2013-09-25 16:42:23 +01:00