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64597f9dae
The patch implements a s390 specific ptrace request PTRACE_TE_ABORT_RAND to modify the randomness of spontaneous aborts of memory transactions of the transaction execution facility. The data argument of the ptrace request is used to specify the levels of randomness, 0 for normal operation, 1 to abort every transaction at a random instruction, and 2 to abort a random transaction at a random instruction. The default is 0 for normal operation. Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Michael Mueller <mimu@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
/*
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* Copyright IBM Corp. 1999, 2009
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*
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#ifndef __ASM_SWITCH_TO_H
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#define __ASM_SWITCH_TO_H
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#include <linux/thread_info.h>
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extern struct task_struct *__switch_to(void *, void *);
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extern void update_cr_regs(struct task_struct *task);
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static inline void save_fp_regs(s390_fp_regs *fpregs)
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{
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asm volatile(
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" std 0,%O0+8(%R0)\n"
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" std 2,%O0+24(%R0)\n"
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" std 4,%O0+40(%R0)\n"
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" std 6,%O0+56(%R0)"
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: "=Q" (*fpregs) : "Q" (*fpregs));
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if (!MACHINE_HAS_IEEE)
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return;
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asm volatile(
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" stfpc %0\n"
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" std 1,%O0+16(%R0)\n"
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" std 3,%O0+32(%R0)\n"
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" std 5,%O0+48(%R0)\n"
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" std 7,%O0+64(%R0)\n"
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" std 8,%O0+72(%R0)\n"
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" std 9,%O0+80(%R0)\n"
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" std 10,%O0+88(%R0)\n"
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" std 11,%O0+96(%R0)\n"
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" std 12,%O0+104(%R0)\n"
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" std 13,%O0+112(%R0)\n"
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" std 14,%O0+120(%R0)\n"
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" std 15,%O0+128(%R0)\n"
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: "=Q" (*fpregs) : "Q" (*fpregs));
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}
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static inline void restore_fp_regs(s390_fp_regs *fpregs)
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{
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asm volatile(
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" ld 0,%O0+8(%R0)\n"
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" ld 2,%O0+24(%R0)\n"
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" ld 4,%O0+40(%R0)\n"
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" ld 6,%O0+56(%R0)"
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: : "Q" (*fpregs));
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if (!MACHINE_HAS_IEEE)
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return;
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asm volatile(
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" lfpc %0\n"
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" ld 1,%O0+16(%R0)\n"
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" ld 3,%O0+32(%R0)\n"
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" ld 5,%O0+48(%R0)\n"
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" ld 7,%O0+64(%R0)\n"
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" ld 8,%O0+72(%R0)\n"
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" ld 9,%O0+80(%R0)\n"
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" ld 10,%O0+88(%R0)\n"
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" ld 11,%O0+96(%R0)\n"
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" ld 12,%O0+104(%R0)\n"
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" ld 13,%O0+112(%R0)\n"
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" ld 14,%O0+120(%R0)\n"
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" ld 15,%O0+128(%R0)\n"
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: : "Q" (*fpregs));
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}
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static inline void save_access_regs(unsigned int *acrs)
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{
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asm volatile("stam 0,15,%0" : "=Q" (*acrs));
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}
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static inline void restore_access_regs(unsigned int *acrs)
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{
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asm volatile("lam 0,15,%0" : : "Q" (*acrs));
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}
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#define switch_to(prev,next,last) do { \
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if (prev->mm) { \
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save_fp_regs(&prev->thread.fp_regs); \
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save_access_regs(&prev->thread.acrs[0]); \
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save_ri_cb(prev->thread.ri_cb); \
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} \
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if (next->mm) { \
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restore_fp_regs(&next->thread.fp_regs); \
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restore_access_regs(&next->thread.acrs[0]); \
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restore_ri_cb(next->thread.ri_cb, prev->thread.ri_cb); \
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update_cr_regs(next); \
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} \
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prev = __switch_to(prev,next); \
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} while (0)
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#define finish_arch_switch(prev) do { \
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set_fs(current->thread.mm_segment); \
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} while (0)
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#endif /* __ASM_SWITCH_TO_H */
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