Alex Deucher 6f15c506e0 drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices ... If the ss clock is external, the CLK_REF bit needs to be set in the SetPixelClock parameters. This should fix DP failures in the channel equalization loop. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@gmail.com>		2011-05-22 20:20:05 +10:00
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drm	drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices	2011-05-22 20:20:05 +10:00
stub	i915: select VIDEO_OUTPUT_CONTROL for ACPI_VIDEO	2011-04-13 09:10:25 +10:00
vga	vga_switcheroo: Remove unbalanced pci_enable_device	2011-05-04 13:46:01 +10:00
Makefile	gpu: Add Intel GMA500(Poulsbo) Stub Driver	2010-10-26 11:00:13 +10:00