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da72a66ba8
The Integrators were using the .nr_irqs field of the machine descriptor to pre-allocate a number of descriptors at boot. This is not right: the irq chip implementations should allocate their descriptors themselves, and as a result the simple irqdomain code warns about it. Get rid of this by just deleting the .nr_irq field from the machine descriptors but take care: doing so makes the default implementation hog the first 16 IRQ numbers, so these cannot be used by the still static IRQ number assignments in the ATAG boot case. So for these, bump the IRQ numbers to begin at 64 and upward. Introduce an offset to offset all IRQ numbers if need be, though we don't expect to do that again as device tree comes along. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
82 lines
3.2 KiB
C
82 lines
3.2 KiB
C
/*
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* arch/arm/mach-integrator/include/mach/irqs.h
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*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* Interrupt numbers, all of the above are just static reservations
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* used so they can be encoded into device resources. They will finally
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* be done away with when switching to device tree.
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*/
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#define IRQ_PIC_START 64
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#define IRQ_SOFTINT (IRQ_PIC_START+0)
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#define IRQ_UARTINT0 (IRQ_PIC_START+1)
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#define IRQ_UARTINT1 (IRQ_PIC_START+2)
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#define IRQ_KMIINT0 (IRQ_PIC_START+3)
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#define IRQ_KMIINT1 (IRQ_PIC_START+4)
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#define IRQ_TIMERINT0 (IRQ_PIC_START+5)
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#define IRQ_TIMERINT1 (IRQ_PIC_START+6)
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#define IRQ_TIMERINT2 (IRQ_PIC_START+7)
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#define IRQ_RTCINT (IRQ_PIC_START+8)
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#define IRQ_AP_EXPINT0 (IRQ_PIC_START+9)
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#define IRQ_AP_EXPINT1 (IRQ_PIC_START+10)
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#define IRQ_AP_EXPINT2 (IRQ_PIC_START+11)
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#define IRQ_AP_EXPINT3 (IRQ_PIC_START+12)
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#define IRQ_AP_PCIINT0 (IRQ_PIC_START+13)
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#define IRQ_AP_PCIINT1 (IRQ_PIC_START+14)
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#define IRQ_AP_PCIINT2 (IRQ_PIC_START+15)
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#define IRQ_AP_PCIINT3 (IRQ_PIC_START+16)
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#define IRQ_AP_V3INT (IRQ_PIC_START+17)
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#define IRQ_AP_CPINT0 (IRQ_PIC_START+18)
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#define IRQ_AP_CPINT1 (IRQ_PIC_START+19)
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#define IRQ_AP_LBUSTIMEOUT (IRQ_PIC_START+20)
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#define IRQ_AP_APCINT (IRQ_PIC_START+21)
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#define IRQ_CP_CLCDCINT (IRQ_PIC_START+22)
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#define IRQ_CP_MMCIINT0 (IRQ_PIC_START+23)
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#define IRQ_CP_MMCIINT1 (IRQ_PIC_START+24)
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#define IRQ_CP_AACIINT (IRQ_PIC_START+25)
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#define IRQ_CP_CPPLDINT (IRQ_PIC_START+26)
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#define IRQ_CP_ETHINT (IRQ_PIC_START+27)
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#define IRQ_CP_TSPENINT (IRQ_PIC_START+28)
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#define IRQ_PIC_END (IRQ_PIC_START+28)
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#define IRQ_CIC_START (IRQ_PIC_END+1)
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#define IRQ_CM_SOFTINT (IRQ_CIC_START+0)
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#define IRQ_CM_COMMRX (IRQ_CIC_START+1)
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#define IRQ_CM_COMMTX (IRQ_CIC_START+2)
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#define IRQ_CIC_END (IRQ_CIC_START+2)
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/*
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* IntegratorCP only
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*/
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#define IRQ_SIC_START (IRQ_CIC_END+1)
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#define IRQ_SIC_CP_SOFTINT (IRQ_SIC_START+0)
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#define IRQ_SIC_CP_RI0 (IRQ_SIC_START+1)
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#define IRQ_SIC_CP_RI1 (IRQ_SIC_START+2)
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#define IRQ_SIC_CP_CARDIN (IRQ_SIC_START+3)
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#define IRQ_SIC_CP_LMINT0 (IRQ_SIC_START+4)
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#define IRQ_SIC_CP_LMINT1 (IRQ_SIC_START+5)
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#define IRQ_SIC_CP_LMINT2 (IRQ_SIC_START+6)
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#define IRQ_SIC_CP_LMINT3 (IRQ_SIC_START+7)
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#define IRQ_SIC_CP_LMINT4 (IRQ_SIC_START+8)
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#define IRQ_SIC_CP_LMINT5 (IRQ_SIC_START+9)
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#define IRQ_SIC_CP_LMINT6 (IRQ_SIC_START+10)
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#define IRQ_SIC_CP_LMINT7 (IRQ_SIC_START+11)
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#define IRQ_SIC_END (IRQ_SIC_START+11)
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