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6ea9cdf391
Two mask registers are used in order to select which events have to actually generate an interrupt on each IRQ line. It seems that in the single-IRQ case it's assumed that the IRQs lines are simply OR-ed, while the two mask registers are still present. The driver still programs the two mask registers separately. However the STM32 variant has only one IRQ, and also has only one mask register. This patch prepares for STM32 variant support by making the driver using only one mask register. This patch also optimize the MMCIMASK1 mask usage by caching it into host->mask1_reg which avoid to read it into mmci_irq(). Tested only on STM32 variant. RFT for variants other than STM32 Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
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