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Existing Qualcomm SoCs have the LPASS pin controller slew rate control in separate register, however this will change with upcoming Qualcomm SoCs. The slew rate will be part of the main register for pin configuration, thus second device IO address space is not needed. Prepare for supporting new SoCs by adding flag customizing the driver behavior for slew rate. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231013145935.220945-3-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
98 lines
2.4 KiB
C
98 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020 Linaro Ltd.
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*/
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#ifndef __PINCTRL_LPASS_LPI_H__
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#define __PINCTRL_LPASS_LPI_H__
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#include <linux/bits.h>
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#include <linux/kernel.h>
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#include "../core.h"
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struct platform_device;
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struct pinctrl_pin_desc;
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#define LPI_SLEW_RATE_CTL_REG 0xa000
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#define LPI_TLMM_REG_OFFSET 0x1000
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#define LPI_SLEW_RATE_MAX 0x03
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#define LPI_SLEW_BITS_SIZE 0x02
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#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
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#define LPI_GPIO_CFG_REG 0x00
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#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
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#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
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#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
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#define LPI_GPIO_OE_MASK BIT(9)
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#define LPI_GPIO_VALUE_REG 0x04
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#define LPI_GPIO_VALUE_IN_MASK BIT(0)
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#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
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#define LPI_GPIO_BIAS_DISABLE 0x0
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#define LPI_GPIO_PULL_DOWN 0x1
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#define LPI_GPIO_KEEPER 0x2
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#define LPI_GPIO_PULL_UP 0x3
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#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
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#define LPI_NO_SLEW -1
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#define LPI_FUNCTION(fname) \
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[LPI_MUX_##fname] = { \
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.name = #fname, \
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.groups = fname##_groups, \
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.ngroups = ARRAY_SIZE(fname##_groups), \
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}
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#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
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{ \
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.group.name = "gpio" #id, \
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.group.pins = gpio##id##_pins, \
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.pin = id, \
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.slew_offset = soff, \
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.group.num_pins = ARRAY_SIZE(gpio##id##_pins), \
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.funcs = (int[]){ \
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LPI_MUX_gpio, \
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LPI_MUX_##f1, \
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LPI_MUX_##f2, \
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LPI_MUX_##f3, \
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LPI_MUX_##f4, \
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}, \
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.nfuncs = 5, \
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}
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/*
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* Slew rate control is done in the same register as rest of the
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* pin configuration.
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*/
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#define LPI_FLAG_SLEW_RATE_SAME_REG BIT(0)
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struct lpi_pingroup {
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struct group_desc group;
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unsigned int pin;
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/* Bit offset in slew register for SoundWire pins only */
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int slew_offset;
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unsigned int *funcs;
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unsigned int nfuncs;
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};
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struct lpi_function {
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const char *name;
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const char * const *groups;
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unsigned int ngroups;
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};
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struct lpi_pinctrl_variant_data {
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const struct pinctrl_pin_desc *pins;
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int npins;
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const struct lpi_pingroup *groups;
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int ngroups;
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const struct lpi_function *functions;
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int nfunctions;
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unsigned int flags;
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};
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int lpi_pinctrl_probe(struct platform_device *pdev);
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void lpi_pinctrl_remove(struct platform_device *pdev);
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#endif /*__PINCTRL_LPASS_LPI_H__*/
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