mirror of
https://github.com/torvalds/linux.git
synced 2024-11-12 15:11:50 +00:00
f8060f5446
This creates irqchip initialization infrastructure from Thomas Petazzoni. The VIC and GIC irqchip code is moved to drivers/irqchips and adapted to use the new infrastructure. All DT enabled platforms using GIC and VIC are converted over to use the new irqchip_init. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJQ8ZobAAoJEMhvYp4jgsXiihIH/2VvxmSHZb0e3jN6AR0B42b7 9EwX0IE0B23t91hNTwdzzmTJQYA7pMmWkgHNfd3vIeqSepJAmrVv/gp4iM9CtPwE KNh+kDWOK2ZsOH4Vb0lYRJHN8WQOIQHuCUr9+MdYLNOgf/pPL6G/Y9kv9A1e7fTC W+tFRjC5N1ilZMGyowX12L1wnwDk6kHzed6YV6bskC17cZ9/pg8PhSVbM4A/3kAv NXYKqbXJb+eCsWGXg/knZXOL6V9gBwvVYoe4O9X3nQ0226AWB9caad8l8tchAjRB fmrYF1tbkpOWPnLxhvQy5b5MJichJgTMJHh7RgiEcc/3f63kOljjlx4QKiqHvT0= =q7gm -----END PGP SIGNATURE----- Merge tag 'gic-vic-to-irqchip' of git://sources.calxeda.com/kernel/linux into next/cleanup From Rob Herring: Initial irqchip init infrastructure and GIC and VIC clean-ups This creates irqchip initialization infrastructure from Thomas Petazzoni. The VIC and GIC irqchip code is moved to drivers/irqchips and adapted to use the new infrastructure. All DT enabled platforms using GIC and VIC are converted over to use the new irqchip_init. * tag 'gic-vic-to-irqchip' of git://sources.calxeda.com/kernel/linux: irqchip: Move ARM vic.h to include/linux/irqchip/arm-vic.h ARM: picoxcell: use common irqchip_init function ARM: spear: use common irqchip_init function irqchip: Move ARM VIC to drivers/irqchip ARM: samsung: remove unused tick.h ARM: remove unneeded vic.h includes ARM: remove mach .handle_irq for VIC users ARM: VIC: set handle_arch_irq in VIC initialization ARM: VIC: shrink down vic.h irqchip: Move ARM gic.h to include/linux/irqchip/arm-gic.h ARM: use common irqchip_init for GIC init irqchip: Move ARM GIC to drivers/irqchip ARM: remove mach .handle_irq for GIC users ARM: GIC: set handle_arch_irq in GIC initialization ARM: GIC: remove direct use of gic_raise_softirq ARM: GIC: remove assembly ifdefs from gic.h ARM: mach-ux500: use SGI0 to wake up the other core arm: add set_handle_irq() to register the parent IRQ controller handler function irqchip: add basic infrastructure irqchip: add to the directories part of the IRQ subsystem in MAINTAINERS Fixed up massive merge conflicts with the timer cleanup due to adjacent changes: Signed-off-by: Olof Johansson <olof@lixom.net> Conflicts: arch/arm/mach-bcm/board_bcm.c arch/arm/mach-cns3xxx/cns3420vb.c arch/arm/mach-ep93xx/adssphere.c arch/arm/mach-ep93xx/edb93xx.c arch/arm/mach-ep93xx/gesbc9312.c arch/arm/mach-ep93xx/micro9.c arch/arm/mach-ep93xx/simone.c arch/arm/mach-ep93xx/snappercl15.c arch/arm/mach-ep93xx/ts72xx.c arch/arm/mach-ep93xx/vision_ep9307.c arch/arm/mach-highbank/highbank.c arch/arm/mach-imx/mach-imx6q.c arch/arm/mach-msm/board-dt-8960.c arch/arm/mach-netx/nxdb500.c arch/arm/mach-netx/nxdkn.c arch/arm/mach-netx/nxeb500hmi.c arch/arm/mach-nomadik/board-nhk8815.c arch/arm/mach-picoxcell/common.c arch/arm/mach-realview/realview_eb.c arch/arm/mach-realview/realview_pb1176.c arch/arm/mach-realview/realview_pb11mp.c arch/arm/mach-realview/realview_pba8.c arch/arm/mach-realview/realview_pbx.c arch/arm/mach-socfpga/socfpga.c arch/arm/mach-spear13xx/spear1310.c arch/arm/mach-spear13xx/spear1340.c arch/arm/mach-spear13xx/spear13xx.c arch/arm/mach-spear3xx/spear300.c arch/arm/mach-spear3xx/spear310.c arch/arm/mach-spear3xx/spear320.c arch/arm/mach-spear3xx/spear3xx.c arch/arm/mach-spear6xx/spear6xx.c arch/arm/mach-tegra/board-dt-tegra20.c arch/arm/mach-tegra/board-dt-tegra30.c arch/arm/mach-u300/core.c arch/arm/mach-ux500/board-mop500.c arch/arm/mach-ux500/cpu-db8500.c arch/arm/mach-versatile/versatile_ab.c arch/arm/mach-versatile/versatile_dt.c arch/arm/mach-versatile/versatile_pb.c arch/arm/mach-vexpress/v2m.c include/asm-generic/vmlinux.lds.h
431 lines
8.8 KiB
C
431 lines
8.8 KiB
C
/*
|
|
* arch/arm/mach-spear6xx/spear6xx.c
|
|
*
|
|
* SPEAr6XX machines common source file
|
|
*
|
|
* Copyright (C) 2009 ST Microelectronics
|
|
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
|
|
*
|
|
* Copyright 2012 Stefan Roese <sr@denx.de>
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*/
|
|
|
|
#include <linux/amba/pl08x.h>
|
|
#include <linux/clk.h>
|
|
#include <linux/err.h>
|
|
#include <linux/irqchip.h>
|
|
#include <linux/of.h>
|
|
#include <linux/of_address.h>
|
|
#include <linux/of_platform.h>
|
|
#include <asm/hardware/pl080.h>
|
|
#include <asm/mach/arch.h>
|
|
#include <asm/mach/time.h>
|
|
#include <asm/mach/map.h>
|
|
#include <plat/pl080.h>
|
|
#include <mach/generic.h>
|
|
#include <mach/spear.h>
|
|
|
|
/* dmac device registration */
|
|
static struct pl08x_channel_data spear600_dma_info[] = {
|
|
{
|
|
.bus_id = "ssp1_rx",
|
|
.min_signal = 0,
|
|
.max_signal = 0,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ssp1_tx",
|
|
.min_signal = 1,
|
|
.max_signal = 1,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "uart0_rx",
|
|
.min_signal = 2,
|
|
.max_signal = 2,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "uart0_tx",
|
|
.min_signal = 3,
|
|
.max_signal = 3,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "uart1_rx",
|
|
.min_signal = 4,
|
|
.max_signal = 4,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "uart1_tx",
|
|
.min_signal = 5,
|
|
.max_signal = 5,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ssp2_rx",
|
|
.min_signal = 6,
|
|
.max_signal = 6,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ssp2_tx",
|
|
.min_signal = 7,
|
|
.max_signal = 7,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ssp0_rx",
|
|
.min_signal = 8,
|
|
.max_signal = 8,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ssp0_tx",
|
|
.min_signal = 9,
|
|
.max_signal = 9,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "i2c_rx",
|
|
.min_signal = 10,
|
|
.max_signal = 10,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "i2c_tx",
|
|
.min_signal = 11,
|
|
.max_signal = 11,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "irda",
|
|
.min_signal = 12,
|
|
.max_signal = 12,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "adc",
|
|
.min_signal = 13,
|
|
.max_signal = 13,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "to_jpeg",
|
|
.min_signal = 14,
|
|
.max_signal = 14,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "from_jpeg",
|
|
.min_signal = 15,
|
|
.max_signal = 15,
|
|
.muxval = 0,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras0_rx",
|
|
.min_signal = 0,
|
|
.max_signal = 0,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras0_tx",
|
|
.min_signal = 1,
|
|
.max_signal = 1,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras1_rx",
|
|
.min_signal = 2,
|
|
.max_signal = 2,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras1_tx",
|
|
.min_signal = 3,
|
|
.max_signal = 3,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras2_rx",
|
|
.min_signal = 4,
|
|
.max_signal = 4,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras2_tx",
|
|
.min_signal = 5,
|
|
.max_signal = 5,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras3_rx",
|
|
.min_signal = 6,
|
|
.max_signal = 6,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras3_tx",
|
|
.min_signal = 7,
|
|
.max_signal = 7,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras4_rx",
|
|
.min_signal = 8,
|
|
.max_signal = 8,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras4_tx",
|
|
.min_signal = 9,
|
|
.max_signal = 9,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras5_rx",
|
|
.min_signal = 10,
|
|
.max_signal = 10,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras5_tx",
|
|
.min_signal = 11,
|
|
.max_signal = 11,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras6_rx",
|
|
.min_signal = 12,
|
|
.max_signal = 12,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras6_tx",
|
|
.min_signal = 13,
|
|
.max_signal = 13,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras7_rx",
|
|
.min_signal = 14,
|
|
.max_signal = 14,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ras7_tx",
|
|
.min_signal = 15,
|
|
.max_signal = 15,
|
|
.muxval = 1,
|
|
.periph_buses = PL08X_AHB1,
|
|
}, {
|
|
.bus_id = "ext0_rx",
|
|
.min_signal = 0,
|
|
.max_signal = 0,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext0_tx",
|
|
.min_signal = 1,
|
|
.max_signal = 1,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext1_rx",
|
|
.min_signal = 2,
|
|
.max_signal = 2,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext1_tx",
|
|
.min_signal = 3,
|
|
.max_signal = 3,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext2_rx",
|
|
.min_signal = 4,
|
|
.max_signal = 4,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext2_tx",
|
|
.min_signal = 5,
|
|
.max_signal = 5,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext3_rx",
|
|
.min_signal = 6,
|
|
.max_signal = 6,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext3_tx",
|
|
.min_signal = 7,
|
|
.max_signal = 7,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext4_rx",
|
|
.min_signal = 8,
|
|
.max_signal = 8,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext4_tx",
|
|
.min_signal = 9,
|
|
.max_signal = 9,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext5_rx",
|
|
.min_signal = 10,
|
|
.max_signal = 10,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext5_tx",
|
|
.min_signal = 11,
|
|
.max_signal = 11,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext6_rx",
|
|
.min_signal = 12,
|
|
.max_signal = 12,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext6_tx",
|
|
.min_signal = 13,
|
|
.max_signal = 13,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext7_rx",
|
|
.min_signal = 14,
|
|
.max_signal = 14,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
}, {
|
|
.bus_id = "ext7_tx",
|
|
.min_signal = 15,
|
|
.max_signal = 15,
|
|
.muxval = 2,
|
|
.periph_buses = PL08X_AHB2,
|
|
},
|
|
};
|
|
|
|
struct pl08x_platform_data pl080_plat_data = {
|
|
.memcpy_channel = {
|
|
.bus_id = "memcpy",
|
|
.cctl_memcpy =
|
|
(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
|
|
PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
|
|
PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
|
|
PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
|
|
PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
|
|
PL080_CONTROL_PROT_SYS),
|
|
},
|
|
.lli_buses = PL08X_AHB1,
|
|
.mem_buses = PL08X_AHB1,
|
|
.get_signal = pl080_get_signal,
|
|
.put_signal = pl080_put_signal,
|
|
.slave_channels = spear600_dma_info,
|
|
.num_slave_channels = ARRAY_SIZE(spear600_dma_info),
|
|
};
|
|
|
|
/*
|
|
* Following will create 16MB static virtual/physical mappings
|
|
* PHYSICAL VIRTUAL
|
|
* 0xF0000000 0xF0000000
|
|
* 0xF1000000 0xF1000000
|
|
* 0xD0000000 0xFD000000
|
|
* 0xFC000000 0xFC000000
|
|
*/
|
|
struct map_desc spear6xx_io_desc[] __initdata = {
|
|
{
|
|
.virtual = VA_SPEAR6XX_ML_CPU_BASE,
|
|
.pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
|
|
.length = 2 * SZ_16M,
|
|
.type = MT_DEVICE
|
|
}, {
|
|
.virtual = VA_SPEAR6XX_ICM1_BASE,
|
|
.pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
|
|
.length = SZ_16M,
|
|
.type = MT_DEVICE
|
|
}, {
|
|
.virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
|
|
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
|
|
.length = SZ_16M,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
|
|
/* This will create static memory mapping for selected devices */
|
|
void __init spear6xx_map_io(void)
|
|
{
|
|
iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
|
|
}
|
|
|
|
void __init spear6xx_timer_init(void)
|
|
{
|
|
char pclk_name[] = "pll3_clk";
|
|
struct clk *gpt_clk, *pclk;
|
|
|
|
spear6xx_clk_init();
|
|
|
|
/* get the system timer clock */
|
|
gpt_clk = clk_get_sys("gpt0", NULL);
|
|
if (IS_ERR(gpt_clk)) {
|
|
pr_err("%s:couldn't get clk for gpt\n", __func__);
|
|
BUG();
|
|
}
|
|
|
|
/* get the suitable parent clock for timer*/
|
|
pclk = clk_get(NULL, pclk_name);
|
|
if (IS_ERR(pclk)) {
|
|
pr_err("%s:couldn't get %s as parent for gpt\n",
|
|
__func__, pclk_name);
|
|
BUG();
|
|
}
|
|
|
|
clk_set_parent(gpt_clk, pclk);
|
|
clk_put(gpt_clk);
|
|
clk_put(pclk);
|
|
|
|
spear_setup_of_timer();
|
|
}
|
|
|
|
/* Add auxdata to pass platform data */
|
|
struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
|
|
OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
|
|
&pl080_plat_data),
|
|
{}
|
|
};
|
|
|
|
static void __init spear600_dt_init(void)
|
|
{
|
|
of_platform_populate(NULL, of_default_bus_match_table,
|
|
spear6xx_auxdata_lookup, NULL);
|
|
}
|
|
|
|
static const char *spear600_dt_board_compat[] = {
|
|
"st,spear600",
|
|
NULL
|
|
};
|
|
|
|
DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
|
|
.map_io = spear6xx_map_io,
|
|
.init_irq = irqchip_init,
|
|
.init_time = spear6xx_timer_init,
|
|
.init_machine = spear600_dt_init,
|
|
.restart = spear_restart,
|
|
.dt_compat = spear600_dt_board_compat,
|
|
MACHINE_END
|