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During Sx->S0 transitions, the interconnect between the MAC and PHY on 82577/82578 can remain in SMBus mode instead of transitioning to the PCIe-like mode required during normal operation. Toggling the LANPHYPC Value bit essentially resets the interconnect forcing it to the correct mode. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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.. | ||
82571.c | ||
defines.h | ||
e1000.h | ||
es2lan.c | ||
ethtool.c | ||
hw.h | ||
ich8lan.c | ||
lib.c | ||
Makefile | ||
netdev.c | ||
param.c | ||
phy.c |