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1081 lines
34 KiB
C
1081 lines
34 KiB
C
/*
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* Copyright 2006 Dave Airlie
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* Copyright 2007 Maarten Maathuis
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* Copyright 2007-2009 Stuart Bennett
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_hw.h"
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#define CHIPSET_NFORCE 0x01a0
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#define CHIPSET_NFORCE2 0x01f0
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/*
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* misc hw access wrappers/control functions
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*/
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void
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NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value)
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{
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NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
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NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value);
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}
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uint8_t
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NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index)
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{
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NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
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return NVReadPRMVIO(dev, head, NV_PRMVIO_SR);
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}
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void
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NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value)
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{
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NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
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NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value);
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}
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uint8_t
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NVReadVgaGr(struct drm_device *dev, int head, uint8_t index)
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{
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NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
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return NVReadPRMVIO(dev, head, NV_PRMVIO_GX);
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}
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/* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
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* it affects only the 8 bit vga io regs, which we access using mmio at
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* 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
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* in general, the set value of cr44 does not matter: reg access works as
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* expected and values can be set for the appropriate head by using a 0x2000
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* offset as required
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* however:
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* a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
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* cr44 must be set to 0 or 3 for accessing values on the correct head
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* through the common 0xc03c* addresses
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* b) in tied mode (4) head B is programmed to the values set on head A, and
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* access using the head B addresses can have strange results, ergo we leave
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* tied mode in init once we know to what cr44 should be restored on exit
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*
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* the owner parameter is slightly abused:
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* 0 and 1 are treated as head values and so the set value is (owner * 3)
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* other values are treated as literal values to set
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*/
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void
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NVSetOwner(struct drm_device *dev, int owner)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (owner == 1)
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owner *= 3;
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if (dev_priv->chipset == 0x11) {
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/* This might seem stupid, but the blob does it and
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* omitting it often locks the system up.
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*/
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NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
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NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX);
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}
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/* CR44 is always changed on CRTC0 */
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NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
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if (dev_priv->chipset == 0x11) { /* set me harder */
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NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
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NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
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}
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}
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void
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NVBlankScreen(struct drm_device *dev, int head, bool blank)
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{
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unsigned char seq1;
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if (nv_two_heads(dev))
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NVSetOwner(dev, head);
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seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
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NVVgaSeqReset(dev, head, true);
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if (blank)
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NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
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else
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NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
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NVVgaSeqReset(dev, head, false);
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}
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/*
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* PLL setting
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*/
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static int
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powerctrl_1_shift(int chip_version, int reg)
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{
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int shift = -4;
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if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
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return shift;
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switch (reg) {
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case NV_RAMDAC_VPLL2:
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shift += 4;
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case NV_PRAMDAC_VPLL_COEFF:
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shift += 4;
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case NV_PRAMDAC_MPLL_COEFF:
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shift += 4;
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case NV_PRAMDAC_NVPLL_COEFF:
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shift += 4;
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}
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/*
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* the shift for vpll regs is only used for nv3x chips with a single
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* stage pll
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*/
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if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
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chip_version == 0x36 || chip_version >= 0x40))
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shift = -4;
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return shift;
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}
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static void
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setPLL_single(struct drm_device *dev, uint32_t reg, struct nouveau_pll_vals *pv)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int chip_version = dev_priv->vbios.chip_version;
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uint32_t oldpll = NVReadRAMDAC(dev, 0, reg);
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int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
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uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
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uint32_t saved_powerctrl_1 = 0;
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int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
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if (oldpll == pll)
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return; /* already set */
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if (shift_powerctrl_1 >= 0) {
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saved_powerctrl_1 = nvReadMC(dev, NV_PBUS_POWERCTRL_1);
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nvWriteMC(dev, NV_PBUS_POWERCTRL_1,
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(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
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1 << shift_powerctrl_1);
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}
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if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
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/* upclock -- write new post divider first */
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NVWriteRAMDAC(dev, 0, reg, pv->log2P << 16 | (oldpll & 0xffff));
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else
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/* downclock -- write new NM first */
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NVWriteRAMDAC(dev, 0, reg, (oldpll & 0xffff0000) | pv->NM1);
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if (chip_version < 0x17 && chip_version != 0x11)
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/* wait a bit on older chips */
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msleep(64);
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NVReadRAMDAC(dev, 0, reg);
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/* then write the other half as well */
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NVWriteRAMDAC(dev, 0, reg, pll);
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if (shift_powerctrl_1 >= 0)
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nvWriteMC(dev, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
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}
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static uint32_t
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new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
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{
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bool head_a = (reg1 == NV_PRAMDAC_VPLL_COEFF);
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if (ss) /* single stage pll mode */
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ramdac580 |= head_a ? NV_RAMDAC_580_VPLL1_ACTIVE :
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NV_RAMDAC_580_VPLL2_ACTIVE;
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else
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ramdac580 &= head_a ? ~NV_RAMDAC_580_VPLL1_ACTIVE :
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~NV_RAMDAC_580_VPLL2_ACTIVE;
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return ramdac580;
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}
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static void
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setPLL_double_highregs(struct drm_device *dev, uint32_t reg1,
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struct nouveau_pll_vals *pv)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int chip_version = dev_priv->vbios.chip_version;
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bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
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uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70);
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uint32_t oldpll1 = NVReadRAMDAC(dev, 0, reg1);
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uint32_t oldpll2 = !nv3035 ? NVReadRAMDAC(dev, 0, reg2) : 0;
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uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
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uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
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uint32_t oldramdac580 = 0, ramdac580 = 0;
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bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
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uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
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int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
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/* model specific additions to generic pll1 and pll2 set up above */
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if (nv3035) {
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pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
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(pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
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pll2 = 0;
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}
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if (chip_version > 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) { /* !nv40 */
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oldramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
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ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
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if (oldramdac580 != ramdac580)
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oldpll1 = ~0; /* force mismatch */
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if (single_stage)
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/* magic value used by nvidia in single stage mode */
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pll2 |= 0x011f;
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}
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if (chip_version > 0x70)
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/* magic bits set by the blob (but not the bios) on g71-73 */
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pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
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if (oldpll1 == pll1 && oldpll2 == pll2)
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return; /* already set */
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if (shift_powerctrl_1 >= 0) {
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saved_powerctrl_1 = nvReadMC(dev, NV_PBUS_POWERCTRL_1);
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nvWriteMC(dev, NV_PBUS_POWERCTRL_1,
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(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
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1 << shift_powerctrl_1);
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}
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if (chip_version >= 0x40) {
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int shift_c040 = 14;
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switch (reg1) {
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case NV_PRAMDAC_MPLL_COEFF:
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shift_c040 += 2;
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case NV_PRAMDAC_NVPLL_COEFF:
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shift_c040 += 2;
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case NV_RAMDAC_VPLL2:
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shift_c040 += 2;
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case NV_PRAMDAC_VPLL_COEFF:
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shift_c040 += 2;
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}
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savedc040 = nvReadMC(dev, 0xc040);
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if (shift_c040 != 14)
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nvWriteMC(dev, 0xc040, savedc040 & ~(3 << shift_c040));
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}
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if (oldramdac580 != ramdac580)
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_580, ramdac580);
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if (!nv3035)
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NVWriteRAMDAC(dev, 0, reg2, pll2);
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NVWriteRAMDAC(dev, 0, reg1, pll1);
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if (shift_powerctrl_1 >= 0)
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nvWriteMC(dev, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
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if (chip_version >= 0x40)
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nvWriteMC(dev, 0xc040, savedc040);
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}
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static void
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setPLL_double_lowregs(struct drm_device *dev, uint32_t NMNMreg,
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struct nouveau_pll_vals *pv)
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{
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/* When setting PLLs, there is a merry game of disabling and enabling
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* various bits of hardware during the process. This function is a
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* synthesis of six nv4x traces, nearly each card doing a subtly
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* different thing. With luck all the necessary bits for each card are
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* combined herein. Without luck it deviates from each card's formula
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* so as to not work on any :)
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*/
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uint32_t Preg = NMNMreg - 4;
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bool mpll = Preg == 0x4020;
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uint32_t oldPval = nvReadMC(dev, Preg);
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uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
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uint32_t Pval = (oldPval & (mpll ? ~(0x11 << 16) : ~(1 << 16))) |
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0xc << 28 | pv->log2P << 16;
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uint32_t saved4600 = 0;
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/* some cards have different maskc040s */
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uint32_t maskc040 = ~(3 << 14), savedc040;
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bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
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if (nvReadMC(dev, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
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return;
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if (Preg == 0x4000)
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maskc040 = ~0x333;
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if (Preg == 0x4058)
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maskc040 = ~(0xc << 24);
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if (mpll) {
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struct pll_lims pll_lim;
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uint8_t Pval2;
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if (get_pll_limits(dev, Preg, &pll_lim))
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return;
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Pval2 = pv->log2P + pll_lim.log2p_bias;
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if (Pval2 > pll_lim.max_log2p)
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Pval2 = pll_lim.max_log2p;
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Pval |= 1 << 28 | Pval2 << 20;
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saved4600 = nvReadMC(dev, 0x4600);
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nvWriteMC(dev, 0x4600, saved4600 | 8 << 28);
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}
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if (single_stage)
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Pval |= mpll ? 1 << 12 : 1 << 8;
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nvWriteMC(dev, Preg, oldPval | 1 << 28);
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nvWriteMC(dev, Preg, Pval & ~(4 << 28));
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if (mpll) {
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Pval |= 8 << 20;
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nvWriteMC(dev, 0x4020, Pval & ~(0xc << 28));
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nvWriteMC(dev, 0x4038, Pval & ~(0xc << 28));
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}
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savedc040 = nvReadMC(dev, 0xc040);
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nvWriteMC(dev, 0xc040, savedc040 & maskc040);
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nvWriteMC(dev, NMNMreg, NMNM);
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if (NMNMreg == 0x4024)
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nvWriteMC(dev, 0x403c, NMNM);
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nvWriteMC(dev, Preg, Pval);
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if (mpll) {
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Pval &= ~(8 << 20);
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nvWriteMC(dev, 0x4020, Pval);
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nvWriteMC(dev, 0x4038, Pval);
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nvWriteMC(dev, 0x4600, saved4600);
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}
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nvWriteMC(dev, 0xc040, savedc040);
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if (mpll) {
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nvWriteMC(dev, 0x4020, Pval & ~(1 << 28));
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nvWriteMC(dev, 0x4038, Pval & ~(1 << 28));
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}
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}
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void
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nouveau_hw_setpll(struct drm_device *dev, uint32_t reg1,
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struct nouveau_pll_vals *pv)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int cv = dev_priv->vbios.chip_version;
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if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
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cv >= 0x40) {
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if (reg1 > 0x405c)
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setPLL_double_highregs(dev, reg1, pv);
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else
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setPLL_double_lowregs(dev, reg1, pv);
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} else
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setPLL_single(dev, reg1, pv);
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}
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/*
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* PLL getting
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*/
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static void
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nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
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uint32_t pll2, struct nouveau_pll_vals *pllvals)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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/* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
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/* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */
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pllvals->log2P = (pll1 >> 16) & 0x7;
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pllvals->N2 = pllvals->M2 = 1;
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if (reg1 <= 0x405c) {
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pllvals->NM1 = pll2 & 0xffff;
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/* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */
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if (!(pll1 & 0x1100))
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pllvals->NM2 = pll2 >> 16;
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} else {
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pllvals->NM1 = pll1 & 0xffff;
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if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
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pllvals->NM2 = pll2 & 0xffff;
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else if (dev_priv->chipset == 0x30 || dev_priv->chipset == 0x35) {
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pllvals->M1 &= 0xf; /* only 4 bits */
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if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
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pllvals->M2 = (pll1 >> 4) & 0x7;
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pllvals->N2 = ((pll1 >> 21) & 0x18) |
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((pll1 >> 19) & 0x7);
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}
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}
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}
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}
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int
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nouveau_hw_get_pllvals(struct drm_device *dev, enum pll_types plltype,
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struct nouveau_pll_vals *pllvals)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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const uint32_t nv04_regs[MAX_PLL_TYPES] = { NV_PRAMDAC_NVPLL_COEFF,
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NV_PRAMDAC_MPLL_COEFF,
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NV_PRAMDAC_VPLL_COEFF,
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NV_RAMDAC_VPLL2 };
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const uint32_t nv40_regs[MAX_PLL_TYPES] = { 0x4000,
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0x4020,
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NV_PRAMDAC_VPLL_COEFF,
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NV_RAMDAC_VPLL2 };
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uint32_t reg1, pll1, pll2 = 0;
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struct pll_lims pll_lim;
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int ret;
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if (dev_priv->card_type < NV_40)
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reg1 = nv04_regs[plltype];
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else
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reg1 = nv40_regs[plltype];
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|
|
pll1 = nvReadMC(dev, reg1);
|
|
|
|
if (reg1 <= 0x405c)
|
|
pll2 = nvReadMC(dev, reg1 + 4);
|
|
else if (nv_two_reg_pll(dev)) {
|
|
uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
|
|
|
|
pll2 = nvReadMC(dev, reg2);
|
|
}
|
|
|
|
if (dev_priv->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
|
|
uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
|
|
|
|
/* check whether vpll has been forced into single stage mode */
|
|
if (reg1 == NV_PRAMDAC_VPLL_COEFF) {
|
|
if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE)
|
|
pll2 = 0;
|
|
} else
|
|
if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE)
|
|
pll2 = 0;
|
|
}
|
|
|
|
nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);
|
|
|
|
ret = get_pll_limits(dev, plltype, &pll_lim);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pllvals->refclk = pll_lim.refclk;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv)
|
|
{
|
|
/* Avoid divide by zero if called at an inappropriate time */
|
|
if (!pv->M1 || !pv->M2)
|
|
return 0;
|
|
|
|
return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
|
|
}
|
|
|
|
int
|
|
nouveau_hw_get_clock(struct drm_device *dev, enum pll_types plltype)
|
|
{
|
|
struct nouveau_pll_vals pllvals;
|
|
|
|
if (plltype == MPLL && (dev->pci_device & 0x0ff0) == CHIPSET_NFORCE) {
|
|
uint32_t mpllP;
|
|
|
|
pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
|
|
if (!mpllP)
|
|
mpllP = 4;
|
|
|
|
return 400000 / mpllP;
|
|
} else
|
|
if (plltype == MPLL && (dev->pci_device & 0xff0) == CHIPSET_NFORCE2) {
|
|
uint32_t clock;
|
|
|
|
pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
|
|
return clock;
|
|
}
|
|
|
|
nouveau_hw_get_pllvals(dev, plltype, &pllvals);
|
|
|
|
return nouveau_hw_pllvals_to_clk(&pllvals);
|
|
}
|
|
|
|
static void
|
|
nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
|
|
{
|
|
/* the vpll on an unused head can come up with a random value, way
|
|
* beyond the pll limits. for some reason this causes the chip to
|
|
* lock up when reading the dac palette regs, so set a valid pll here
|
|
* when such a condition detected. only seen on nv11 to date
|
|
*/
|
|
|
|
struct pll_lims pll_lim;
|
|
struct nouveau_pll_vals pv;
|
|
uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
|
|
|
|
if (get_pll_limits(dev, head ? VPLL2 : VPLL1, &pll_lim))
|
|
return;
|
|
nouveau_hw_get_pllvals(dev, head ? VPLL2 : VPLL1, &pv);
|
|
|
|
if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
|
|
pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
|
|
pv.log2P <= pll_lim.max_log2p)
|
|
return;
|
|
|
|
NV_WARN(dev, "VPLL %d outwith limits, attempting to fix\n", head + 1);
|
|
|
|
/* set lowest clock within static limits */
|
|
pv.M1 = pll_lim.vco1.max_m;
|
|
pv.N1 = pll_lim.vco1.min_n;
|
|
pv.log2P = pll_lim.max_usable_log2p;
|
|
nouveau_hw_setpll(dev, pllreg, &pv);
|
|
}
|
|
|
|
/*
|
|
* vga font save/restore
|
|
*/
|
|
|
|
static void nouveau_vga_font_io(struct drm_device *dev,
|
|
void __iomem *iovram,
|
|
bool save, unsigned plane)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
unsigned i;
|
|
|
|
NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane);
|
|
NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane);
|
|
for (i = 0; i < 16384; i++) {
|
|
if (save) {
|
|
dev_priv->saved_vga_font[plane][i] =
|
|
ioread32_native(iovram + i * 4);
|
|
} else {
|
|
iowrite32_native(dev_priv->saved_vga_font[plane][i],
|
|
iovram + i * 4);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save)
|
|
{
|
|
uint8_t misc, gr4, gr5, gr6, seq2, seq4;
|
|
bool graphicsmode;
|
|
unsigned plane;
|
|
void __iomem *iovram;
|
|
|
|
if (nv_two_heads(dev))
|
|
NVSetOwner(dev, 0);
|
|
|
|
NVSetEnablePalette(dev, 0, true);
|
|
graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1;
|
|
NVSetEnablePalette(dev, 0, false);
|
|
|
|
if (graphicsmode) /* graphics mode => framebuffer => no need to save */
|
|
return;
|
|
|
|
NV_INFO(dev, "%sing VGA fonts\n", save ? "Sav" : "Restor");
|
|
|
|
/* map first 64KiB of VRAM, holds VGA fonts etc */
|
|
iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536);
|
|
if (!iovram) {
|
|
NV_ERROR(dev, "Failed to map VRAM, "
|
|
"cannot save/restore VGA fonts.\n");
|
|
return;
|
|
}
|
|
|
|
if (nv_two_heads(dev))
|
|
NVBlankScreen(dev, 1, true);
|
|
NVBlankScreen(dev, 0, true);
|
|
|
|
/* save control regs */
|
|
misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ);
|
|
seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX);
|
|
seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX);
|
|
gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX);
|
|
gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX);
|
|
gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX);
|
|
|
|
NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67);
|
|
NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);
|
|
NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0);
|
|
NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5);
|
|
|
|
/* store font in planes 0..3 */
|
|
for (plane = 0; plane < 4; plane++)
|
|
nouveau_vga_font_io(dev, iovram, save, plane);
|
|
|
|
/* restore control regs */
|
|
NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc);
|
|
NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4);
|
|
NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5);
|
|
NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6);
|
|
NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);
|
|
NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);
|
|
|
|
if (nv_two_heads(dev))
|
|
NVBlankScreen(dev, 1, false);
|
|
NVBlankScreen(dev, 0, false);
|
|
|
|
iounmap(iovram);
|
|
}
|
|
|
|
/*
|
|
* mode state save/load
|
|
*/
|
|
|
|
static void
|
|
rd_cio_state(struct drm_device *dev, int head,
|
|
struct nv04_crtc_reg *crtcstate, int index)
|
|
{
|
|
crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index);
|
|
}
|
|
|
|
static void
|
|
wr_cio_state(struct drm_device *dev, int head,
|
|
struct nv04_crtc_reg *crtcstate, int index)
|
|
{
|
|
NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
|
|
}
|
|
|
|
static void
|
|
nv_save_state_ramdac(struct drm_device *dev, int head,
|
|
struct nv04_mode_state *state)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
|
|
int i;
|
|
|
|
if (dev_priv->card_type >= NV_10)
|
|
regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
|
|
|
|
nouveau_hw_get_pllvals(dev, head ? VPLL2 : VPLL1, ®p->pllvals);
|
|
state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
|
|
if (nv_two_heads(dev))
|
|
state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
|
|
if (dev_priv->chipset == 0x11)
|
|
regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
|
|
|
|
regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
|
|
|
|
if (nv_gf4_disp_arch(dev))
|
|
regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
|
|
if (dev_priv->chipset >= 0x30)
|
|
regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
|
|
|
|
regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
|
|
regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
|
|
regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
|
|
regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
|
|
regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
|
|
regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
|
|
regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
|
|
regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
|
|
|
|
for (i = 0; i < 7; i++) {
|
|
uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
|
|
regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
|
|
regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
|
|
}
|
|
|
|
if (nv_gf4_disp_arch(dev)) {
|
|
regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
|
|
for (i = 0; i < 3; i++) {
|
|
regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
|
|
regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
|
|
}
|
|
}
|
|
|
|
regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
|
|
regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
|
|
if (!nv_gf4_disp_arch(dev) && head == 0) {
|
|
/* early chips don't allow access to PRAMDAC_TMDS_* without
|
|
* the head A FPCLK on (nv11 even locks up) */
|
|
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &
|
|
~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK);
|
|
}
|
|
regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
|
|
regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
|
|
|
|
regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
|
|
|
|
if (nv_gf4_disp_arch(dev))
|
|
regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
|
|
|
|
if (dev_priv->card_type == NV_40) {
|
|
regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
|
|
regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
|
|
regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
|
|
|
|
for (i = 0; i < 38; i++)
|
|
regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
|
|
NV_PRAMDAC_CTV + 4*i);
|
|
}
|
|
}
|
|
|
|
static void
|
|
nv_load_state_ramdac(struct drm_device *dev, int head,
|
|
struct nv04_mode_state *state)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
|
|
uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
|
|
int i;
|
|
|
|
if (dev_priv->card_type >= NV_10)
|
|
NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
|
|
|
|
nouveau_hw_setpll(dev, pllreg, ®p->pllvals);
|
|
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
|
|
if (nv_two_heads(dev))
|
|
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
|
|
if (dev_priv->chipset == 0x11)
|
|
NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
|
|
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
|
|
|
|
if (nv_gf4_disp_arch(dev))
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
|
|
if (dev_priv->chipset >= 0x30)
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
|
|
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
|
|
|
|
for (i = 0; i < 7; i++) {
|
|
uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
|
|
|
|
NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
|
|
NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
|
|
}
|
|
|
|
if (nv_gf4_disp_arch(dev)) {
|
|
NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
|
|
for (i = 0; i < 3; i++) {
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
|
|
}
|
|
}
|
|
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
|
|
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
|
|
|
|
if (nv_gf4_disp_arch(dev))
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
|
|
|
|
if (dev_priv->card_type == NV_40) {
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
|
|
NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
|
|
|
|
for (i = 0; i < 38; i++)
|
|
NVWriteRAMDAC(dev, head,
|
|
NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
|
|
}
|
|
}
|
|
|
|
static void
|
|
nv_save_state_vga(struct drm_device *dev, int head,
|
|
struct nv04_mode_state *state)
|
|
{
|
|
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
|
|
int i;
|
|
|
|
regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
|
|
|
|
for (i = 0; i < 25; i++)
|
|
rd_cio_state(dev, head, regp, i);
|
|
|
|
NVSetEnablePalette(dev, head, true);
|
|
for (i = 0; i < 21; i++)
|
|
regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
|
|
NVSetEnablePalette(dev, head, false);
|
|
|
|
for (i = 0; i < 9; i++)
|
|
regp->Graphics[i] = NVReadVgaGr(dev, head, i);
|
|
|
|
for (i = 0; i < 5; i++)
|
|
regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
|
|
}
|
|
|
|
static void
|
|
nv_load_state_vga(struct drm_device *dev, int head,
|
|
struct nv04_mode_state *state)
|
|
{
|
|
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
|
|
int i;
|
|
|
|
NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
|
|
|
|
for (i = 0; i < 5; i++)
|
|
NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
|
|
|
|
nv_lock_vga_crtc_base(dev, head, false);
|
|
for (i = 0; i < 25; i++)
|
|
wr_cio_state(dev, head, regp, i);
|
|
nv_lock_vga_crtc_base(dev, head, true);
|
|
|
|
for (i = 0; i < 9; i++)
|
|
NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
|
|
|
|
NVSetEnablePalette(dev, head, true);
|
|
for (i = 0; i < 21; i++)
|
|
NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
|
|
NVSetEnablePalette(dev, head, false);
|
|
}
|
|
|
|
static void
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nv_save_state_ext(struct drm_device *dev, int head,
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struct nv04_mode_state *state)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv04_crtc_reg *regp = &state->crtc_reg[head];
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int i;
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rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
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if (dev_priv->card_type >= NV_30)
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rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
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if (dev_priv->card_type >= NV_10) {
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regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
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regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
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if (dev_priv->card_type >= NV_30)
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regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
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if (dev_priv->card_type == NV_40)
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regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
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if (nv_two_heads(dev))
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regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
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regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
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}
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regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
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if (dev_priv->card_type >= NV_10) {
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rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
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}
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/* NV11 and NV20 don't have this, they stop at 0x52. */
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if (nv_gf4_disp_arch(dev)) {
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rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
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for (i = 0; i < 0x10; i++)
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regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
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}
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regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
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}
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static void
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nv_load_state_ext(struct drm_device *dev, int head,
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struct nv04_mode_state *state)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv04_crtc_reg *regp = &state->crtc_reg[head];
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uint32_t reg900;
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int i;
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if (dev_priv->card_type >= NV_10) {
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if (nv_two_heads(dev))
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/* setting ENGINE_CTRL (EC) *must* come before
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* CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
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* EC that should not be overwritten by writing stale EC
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*/
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NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
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nvWriteVIDEO(dev, NV_PVIDEO_STOP, 1);
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nvWriteVIDEO(dev, NV_PVIDEO_INTR_EN, 0);
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nvWriteVIDEO(dev, NV_PVIDEO_OFFSET_BUFF(0), 0);
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nvWriteVIDEO(dev, NV_PVIDEO_OFFSET_BUFF(1), 0);
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nvWriteVIDEO(dev, NV_PVIDEO_LIMIT(0), dev_priv->fb_available_size - 1);
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nvWriteVIDEO(dev, NV_PVIDEO_LIMIT(1), dev_priv->fb_available_size - 1);
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nvWriteVIDEO(dev, NV_PVIDEO_UVPLANE_LIMIT(0), dev_priv->fb_available_size - 1);
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nvWriteVIDEO(dev, NV_PVIDEO_UVPLANE_LIMIT(1), dev_priv->fb_available_size - 1);
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nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
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NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
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NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
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NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
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if (dev_priv->card_type >= NV_30)
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NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
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if (dev_priv->card_type == NV_40) {
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NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
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reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
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if (regp->crtc_cfg == NV_PCRTC_CONFIG_START_ADDRESS_HSYNC)
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
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else
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
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}
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}
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NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
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if (dev_priv->card_type >= NV_30)
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wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
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if (dev_priv->card_type == NV_40)
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nv_fix_nv40_hw_cursor(dev, head);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
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if (dev_priv->card_type >= NV_10) {
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wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
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}
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/* NV11 and NV20 stop at 0x52. */
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if (nv_gf4_disp_arch(dev)) {
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if (dev_priv->card_type == NV_10) {
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/* Not waiting for vertical retrace before modifying
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CRE_53/CRE_54 causes lockups. */
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nouveau_wait_until(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
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nouveau_wait_until(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
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}
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wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
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for (i = 0; i < 0x10; i++)
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NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
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}
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NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
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/* Setting 1 on this value gives you interrupts for every vblank period. */
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NVWriteCRTC(dev, head, NV_PCRTC_INTR_EN_0, 0);
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NVWriteCRTC(dev, head, NV_PCRTC_INTR_0, NV_PCRTC_INTR_0_VBLANK);
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}
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static void
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nv_save_state_palette(struct drm_device *dev, int head,
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struct nv04_mode_state *state)
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{
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int head_offset = head * NV_PRMDIO_SIZE, i;
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nv_wr08(dev, NV_PRMDIO_PIXEL_MASK + head_offset,
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NV_PRMDIO_PIXEL_MASK_MASK);
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nv_wr08(dev, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
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for (i = 0; i < 768; i++) {
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state->crtc_reg[head].DAC[i] = nv_rd08(dev,
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NV_PRMDIO_PALETTE_DATA + head_offset);
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}
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NVSetEnablePalette(dev, head, false);
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}
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void
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nouveau_hw_load_state_palette(struct drm_device *dev, int head,
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struct nv04_mode_state *state)
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{
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int head_offset = head * NV_PRMDIO_SIZE, i;
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nv_wr08(dev, NV_PRMDIO_PIXEL_MASK + head_offset,
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NV_PRMDIO_PIXEL_MASK_MASK);
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nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
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for (i = 0; i < 768; i++) {
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nv_wr08(dev, NV_PRMDIO_PALETTE_DATA + head_offset,
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state->crtc_reg[head].DAC[i]);
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}
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NVSetEnablePalette(dev, head, false);
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}
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|
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void nouveau_hw_save_state(struct drm_device *dev, int head,
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struct nv04_mode_state *state)
|
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{
|
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struct drm_nouveau_private *dev_priv = dev->dev_private;
|
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|
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if (dev_priv->chipset == 0x11)
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/* NB: no attempt is made to restore the bad pll later on */
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nouveau_hw_fix_bad_vpll(dev, head);
|
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nv_save_state_ramdac(dev, head, state);
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nv_save_state_vga(dev, head, state);
|
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nv_save_state_palette(dev, head, state);
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nv_save_state_ext(dev, head, state);
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}
|
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|
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void nouveau_hw_load_state(struct drm_device *dev, int head,
|
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struct nv04_mode_state *state)
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{
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NVVgaProtect(dev, head, true);
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nv_load_state_ramdac(dev, head, state);
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nv_load_state_ext(dev, head, state);
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nouveau_hw_load_state_palette(dev, head, state);
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nv_load_state_vga(dev, head, state);
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NVVgaProtect(dev, head, false);
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}
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